High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

Abstract

This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

Review of Joint Radar, Communication, and Integration of Beam-forming Technology

“…Significant data transfer between vehicles via virtual reality videos and the system is fundamental regarding the communication setup. The author in [187] introduces a faster method for sending high-quality VR content over wireless networks using advanced error-correcting techniques. It can fix many errors in the data and send up to 4K video at speeds of 12.8 Gbps, all with a very low delay of just 1 ms, making VR experiences smoother and more immersive.…”

Computational Power Evaluation for Energy-Constrained Wireless Communications Systems

“…Power consumption was estimated from the synthesized design using synthesis Design Compiler tools from Synopsys. It is worth noting that the 65 nm technology has been widely considered for the design of various wireless communications systems as reported in [37] and the references listed therein. The codes we used for implementation of mathematical operations on FPGAs were synthesized with very few modifications to suite the ASIC implementation.…”

Complexity Reduction of MLSE and MAP Equalizers Using Modified Prolate Basis Expansion

“…However, OFDM has two major drawbacks: high sensitivity to Doppler spread, dependent on the system's mobility, and a high peak-to-average power ratio (PAPR), proportional to the length of the Fourier transform. In high carrier frequency bands (e.g., 60-70 GHz), even a small movement in the transceivers can cause a high Doppler spread, provoking intercarrier interference and long transmission latencies [1]. To avoid excessive PAPR while complexity equalization remains low in the frequency domain, the discrete-Fourier-transform (DFT)-Spread OFDM has been employed.…”