High throughput and low power dissipation in QCA pipelines using Bennett clocking

Abstract

Abstract-This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA. I. INTRODUCTIONAmong so-called emerging technologies that have been proposed to overcome the limitations of CMOS at the "end of the technology roadmap", Quantum-dot Cellular Automata (QCA) shows features that are very promising to achieve both high computational throughput and low power dissipation In addition to great promise due to its small size and high computational speed, it has been shown that QCA has great potential for low power operation. The reversible computational paradigm is particularly well suited to QCA because Timler has shown that in a clocked, information preserving system, the energy dissipation of a QCA circuit can be significantly lower than k B T ln2 [9]. Reversible computation is drawing increasing interest as a low power computation paradigm because it may overcome the fundamental power limitation