High throughput Cholesky decomposition based on FPGA

Luo, Jun; Huang, Qijun; Chang, Sheng; Song, Xiuxian; Shang, Yun

doi:10.1109/cisp.2013.6743941

Cited by 6 publications

(6 citation statements)

References 10 publications

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“…It can be seen that the proposed M4 shows the best throughput performance in Table III. It achieves nearly 42 % throughput improvement over previous work [18]. The throughput improvement in M4 is obtained at the cost of a high complexity (9.8 % of more Adaptive Look-up Tables (ALUTs) and 9 of more multipliers).…”

Section: B Application In Cholesky Decompositionmentioning

confidence: 90%

“…The throughput ( T ) is determined by (8), where S denotes the input samples per cycle, and max f is the maximum frequency (Fmax in Table III). In Table III, M0 is the anchor Cholesky decomposition based on IP [18]. M1, M11, M3 and M4 denote the Cholesky decomposition using corresponding method in Table II.…”

Section: B Application In Cholesky Decompositionmentioning

confidence: 99%

“…It can reach a precision of 10 -3 at four segments while 10 -5 of precision can be obtained in this paper at the same segments. Compared to [18], the proposed architecture leads to 42 % of throughput improvement when applied in Cholesky decomposition.…”

Section: Comparisonmentioning

confidence: 99%

See 2 more Smart Citations

Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

Luo¹,

Huang²,

Luo³

et al. 2017

ElAEE

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Inverse square root has played an important role in Cholesky decomposition, which devoted to hardware efficient compressed sensing. However, the performance is usually limited by the trade-off between throughput and precision. This paper presents hardware implementation of fixed-point single iterated multiplicative inverse square root. Multiple piecewise linear approximation in softly nonlinear range is used to compute the initial value. Single iterated Newton-Raphson method is employed to obtain high precision. Multiple constants multiplication technique is proposed to achieve high throughput. The combination of these techniques yields high performance in terms of throughput and precision. It obtains more than 70 % of throughput improvement and almost 100 × higher precision over the inverse square root Intellectual Property (IP) from Altera. In addition, Cholesky decomposition has been presented to validate the proposed architecture, which shows that 42 % of throughput improvement is achieved compared with the IP.

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Section: B Application In Cholesky Decompositionmentioning

confidence: 90%

Section: B Application In Cholesky Decompositionmentioning

confidence: 99%

See 1 more Smart Citation

Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

Luo¹,

Huang²,

Luo³

et al. 2017

ElAEE

Self Cite

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“…Arithmetic element functions are playing very important roles in wireless communication, computer graphics and digital signal processing, reciprocal is one of these functions which are frequently computed in matrix operations [1]. Because of the characteristic of high throughput and low latency, hardware implementation has become a main approach in computing acceleration.…”

Section: Introductionmentioning

confidence: 99%

Hardware Efficient Reciprocal Using Second Order Harmonized Parabolic Synthesis and Squaring Shrunk Method

Luo¹,

Luo²,

Yang³

et al. 2018

ElAEE

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In applications as in wireless communication, computer graphics and digital signal processing, a massive of complex matrix operations is often performed. Reciprocal is computed in large quantities in these matrix operations. To obtain high performance, efficient algorithm and hardware architecture are important in terms of low cost, low computation time and high precision. Second order first sub-function and squaring shrunk method have been proposed to build efficient hardware architecture for reciprocal using field programmable gate array. Second order first sub-function in harmonized parabolic synthesis is presented to improve the approximating precision and decrease the memory usage at the cost of additional multipliers. To further reduce the complexity, squaring shrunk method is proposed to decrease the expensive cost of multipliers. The combination of these techniques yields good performance trade-off. Precision simulation and hardware implementation result has shown that hardware reciprocal of high precision, low memory and low multiplier usage has been obtained compared to traditional first order first sub-function harmonized parabolic synthesis method.

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“…The complexity of the direct analytic method increases exponentially with the size of matrix, so matrix decom-position becomes the most common method applied in matrix inversion with large dimensions, such as LU decomposition (with partial pivoting) [4,5,6,7], QR decomposition [8,9,10], Cholesky decomposition [11], etc. By analyzing these algorithms [12], LU decomposition (with partial pivoting) has better generality than Cholesky decomposition which only applies to symmetric positive definite matrices, and lower computational complexity than QR decomposition.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of high performance matrix inversion based on reconfigurable processor

Wang

Feng

et al. 2016

IEICE Electron. Express

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In this paper, we propose a high performance matrix inversion implementation on a reconfigurable application specific processor. Our implementation can accelerate variable order matrix inversion ranging from 4 to 144. We adopt LU decomposition to reduce the computation complexity and a pivoting operation to ensure the stability. In order to get higher performance within the limited resources, parallel computing and timesharing multiplexing are employed. The chip testing results show that our implementation improve the performance of inversion efficiently. The highest parallel speed-up ratio can achieve 3 times, and the execution time of a 144 × 144 matrix inversion is 4.07 ms.

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High throughput Cholesky decomposition based on FPGA

Cited by 6 publications

References 10 publications

Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

Hardware Efficient Reciprocal Using Second Order Harmonized Parabolic Synthesis and Squaring Shrunk Method

Design and implementation of high performance matrix inversion based on reconfigurable processor

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