High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder

Abstract

Abstract-To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits the achievable throughput in the parallel decoders due to the massive memory conflicts. In this paper, we propose a flexible Double-Buffer based Contention-Free (DBCF) interleaver architecture that can efficiently solve the memory conflict problem for parallel turbo decoders with very high parallelism. The proposed DBCF architecture enables high throughput concurrent interleaving for multi-standard turbo decoders that support UMTS/HSPA+, LTE and WiMAX, with small datapath delays and low hardware cost. We implemented the DBCF interleaver with a 65nm CMOS technology. The implementation of this highly efficient DBCF interleaver architecture shows significant improvement in terms of the maximum throughput and occupied chip area compared to the previous work.

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

“…1, if more than one SISO decoder tries to access the same memory module, a memory conflict occurs. The ratio of memory conflicts increases exponentially as the parallelism goes higher [12,13]. To solve the memory conflict problem, extra clock cycles need to be spent, which prevent the turbo decoder from achieving high data rate.…”

“…In addition, researchers in [12] mentioned that memory reordering may be used to solve the memory reading conflict problem, but the reordering logic will add too much overhead to the memory control blocks. To solve the aforementioned problems, we propose a new scheduling scheme which allows us to utilize an efficient buffer architecture proposed in our previous work [13].…”

“…2-(a)), we can utilize buffer structures such as double-buffer contention-free (DBCF) architecture as a "write conflict solver" to cache the data accesses and to balance the memory access workloads among memory modules [13]. All the SISO decoders can still keep full-speed processing so that the overall high throughput can be guaranteed.…”

“…First of all, the memory writing conflict is easier to solve than the memory reading conflict. We can use efficient buffer structures such as DBCF to solve the memory writing conflict in both half iterations while maintaining high throughput [13]. Second, without memory reading conflict, we can remove the read conflict solver hardware from the interleaver.…”

“…Fig. 5 shows the architecture of a complete parallel interleaver solution, combining the proposed parallel IAG and an efficient memory writing conflict solver called DBCF buffer [13]. This architecture can efficiently generate interleaving addresses on-the-fly and effectively solve the memory conflict problem using low complexity hardware for highly parallel turbo decoders.…”