High throughput FPGA implementation of Reed-Solomon Encoder for Space Data Systems

Garg, Dimple; Sharma, Chetan; Chaurasia, Pratap; Chowdhury, A. R.

doi:10.1109/nuicone.2013.6780107

Cited by 3 publications

(2 citation statements)

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“…For the field GF [15][16]the corresponding primitive polynomial [17][18] is the following in the table 1 The minimum [19] RS code defines the number of symbols distance between two RS code words:…”

Section: Primitive Polynomialmentioning

confidence: 99%

Development and Validation of an optimized syndromes block for reed solomon decoder

Mohamed,

Azeddine,

Anas El Habti

et al. 2023

ITM Web Conf.

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Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.

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Section: Primitive Polynomialmentioning

confidence: 99%

Development and Validation of an optimized syndromes block for reed solomon decoder

Mohamed,

Azeddine,

Anas El Habti

et al. 2023

ITM Web Conf.

View full text Add to dashboard Cite

show abstract

“…Several proposals of RTL architectures for RS codecs are depicted in literature. The majority of them are designed for specific applications such as wireless networks [21,22], digital television [23], and space data systems [24]. They are usually regulated by standards that specify which parametric configurations must be used in the RS codec implementation.…”

Section: Related Workmentioning

confidence: 99%

RTL development of a parameterizable Reed–Solomon Codec

Silva

Silvano

Duarte

2021

IET Computers & Digital Tech

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Error correction coding (ECC) methods have been considered essential constituents of data transmission systems. Reed–Solomon (RS) codes are a core ECC technique that have been adopted in numerous applications and standards. Several register‐transfer level (RTL) architectures for RS codecs have been proposed to address specific demands and overcome scalability challenges in speed and area. However, the influence of the main RS codec parameters on the corresponding hardware design has been undervalued by literature. The authors propose an open access intellectual property (IP) of a parameterizable RS codec and explore key aspects of its RTL development using IEEE 802.15.7 standard as illustration. Herein, it is demonstrated that formal verification has the potential to be solely used to attest the correctness of the developed IP for the RS codec configurations specified by IEEE 802.15.7. Furthermore, synthesis reports for the target field‐programmable gate array devices indicate that the proposed IP is able to cope with throughput requirements in IEEE 802.15.7.

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