High-throughput, low-memory applications on the Pica architecture

Wills, D.S.; Cat, H.H.; Cruz-Rivera, J.L.; Lacy, W.S.; Baker, J.M.; Eble, John; Lopez-Lagunas, A.; Hopper, M.

doi:10.1109/71.629488

Cited by 8 publications

(2 citation statements)

References 32 publications

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“…Some of the message traffic workload parameters used in this paper were collected from applications running on a message passing architecture (PICA) being developed at Georgia Tech [17]. The application suite includes both scientific and image processing programs running on system configurations of 100 to 4,000 nodes.…”

Section: Traffic Workloadmentioning

confidence: 99%

HiPER: a compact narrow channel router with hop-by-hop error correction

May

Bunchua

Wills

2002

IEEE Trans. Parallel Distrib. Syst.

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Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communicate at significantly higher speeds while operating more efficiently to meet system size, weight, power, and energy requirements. As high-performance parallel computing architectures make their way into portable systems, compact, efficient, and error-tolerant computing and communication mechanisms will be required. This paper presents the High-Performance Efficient Router (HiPER), an efficient multidimensional router supporting high-throughput errorcorrected communication channels. HiPER is a proof-of-concept vehicle for efficient implementations of routing, switching, and error control mechanisms. It combines mad postman (bit-pipelined) switching with dimension-order routing, producing a low-latency routing router that is less sensitive to message distance than a word parallel crossbar router. To maintain robust communication as link speeds increase and link power budgets decrease, HiPER employs flit-level hop-by-hop retransmission of erroneous flits, which provides builtin error control at the network level. Data presented on the implemented bit serial version of HiPER offer insight into future router designs with channel sizes between bit-serial and word-wide.

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Section: Traffic Workloadmentioning

confidence: 99%

HiPER: a compact narrow channel router with hop-by-hop error correction

May

Bunchua

Wills

2002

IEEE Trans. Parallel Distrib. Syst.

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“…The characteristics of the traces are given in Table 4, where the problem size refers to: the number of elements in the grid partitioning for thermal relaxation, the number of elements in the matrices multiplied in matrix multiplication, the number of pixels in the compressed image in JPEG, and the number of pixels in the reconstructed image in PET. More details regarding the actual parallelization of these applications can be found in [51].…”

Section: Trace-driven Trafficmentioning

confidence: 99%

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

Lacy

Cruz-Rivera

Wills

1998

IEEE Trans. Parallel Distrib. Syst.

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Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology, it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.

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