High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation

Domanski, Robson; Goebel, Jones; Penny, Wagner; Porto, Marcelo; Palomino, Daniel; Zatt, Bruno; Agostini, Luciano

doi:10.1109/tcsii.2019.2909705

Cited by 24 publications

(22 citation statements)

References 11 publications

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“…As discussed before, only two related works were found in the literature reporting hardware solutions for the AV1 interpolation, both with two implementations [16] [17]. The work in [16] is focused in the motion compensation, and the work in [17] supports only the Regular filters family for the fractional motion estimation. As discussed before, these related works do not employ approximate computing.…”

Section: Coding Efficiency and Synthesis Resultsmentioning

confidence: 99%

“…From Table IV one can observe that the FME interpolation architecture using the AAFF filter dissipates more power and uses more area than [16]. This occurs because our architecture aims at higher throughput to support the FME processing requirements, whereas the related work focuses on the MC throughput.…”

Section: Coding Efficiency and Synthesis Resultsmentioning

confidence: 99%

“…On the other hand, some works in the literature target hardware designs for the AV1 interpolation filters. The work in [16] is focused in the motion compensation, where the work [17] is focused in the fractional motion estimation, but supporting only a few filters. Both works do not explore approximate computing.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation

Domanski

Kolodziejski²,

Corrêa

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Modern video encoders like the AOM Video 1 (AV1) implement several complex tools to allow the required high level of compression efficiency. The Fractional Motion Estimation (FME) is one of these tools and in AV1 the FME defines 90 different filters. To handle such complexity, hardware acceleration using approximate computing has become an alternative to be explored. This paper presents an approximate solution for the AV1 FME interpolation filters based on the approximation of the original filter coefficients intending to generate more hardware friendly coefficients. The approximated version was designed in hardware and can achieve real-time interpolation for UHD 8K videos at 30 frames per second, when synthesized using 40nm TSMC standard-cells technology. The designed architecture dissipates 26.79mW which represents more than 80% power reduction when compared to the original precise solution. The approximation implied in a small average coding efficiency degradation of 0.54% in BD-BR. When comparing with related works, this architecture reaches an expressive power reduction (2.1 to 4.8 times) even supporting more complex tools.

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Section: Coding Efficiency and Synthesis Resultsmentioning

confidence: 99%

Section: Coding Efficiency and Synthesis Resultsmentioning

confidence: 99%

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Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation

Domanski

Kolodziejski²,

Corrêa

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

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show abstract

“…In [58], the level of parallelism is configurable, ranging from 4 to 128 samples per cycle. Because of this, the authors reported a throughput of UHD 8K at 120 fps, which is much higher than what was achieved by [57], but at the cost of a higher gate count and power dissipation.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 87%

“…Domanski et al [57] and Freitas et al [58] presented architectures for the subpixel interpolation filter present in the inter prediction module of the decoder. In [57], the samplelevel parallelism of the architecture allows the processing of any block size as subblocks of size 4×4 (16 samples per cycle), but since it is a decoder design, only one of the many supported filters is used per predicted block (the one signaled in the bitstream). The authors reported a throughput of UHD 8K at 30 fps.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

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This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

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An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs

Saldanha

Corrêa

et al. 2020

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation

Cited by 24 publications

References 11 publications

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs

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