High-Throughput Radix-4 logMAP Turbo Decoder Architecture

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.

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“…For binary turbo codes, the trellis cycles can be reduced 50% by applying the one-level look-ahead recursion [6] [7] as illustrated in Fig. 2.…”

Section: Unified Radix-4 Decoding Algorithmmentioning

confidence: 99%

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

Sun

Zhu

Goel

et al. 2008

2008 International Conference on Application-Specific Systems, Architectures and Processors

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“…However, the recursions involve calculations that must be performed in series. Therefore, conventional architectures typically employ additional hardware 1 during synthesis to achieve a short critical path, a high clock frequency and a high throughput [24]. A number of variants of the LUT-Log-BCJR architecture of Figure 2 have been proposed for further increasing the decoding throughput.…”

Section: Conventional Lut-log-bcjr Architecturementioning

confidence: 99%

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

Maunder

Al-Hashimi

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, Look-Up- Table-Log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental Add Compare Select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of-the-art Maximum Logarithmic Bahl-Cocke-Jelinek-Raviv (Max-Log-BCJR) implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m.

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“…Radix-4 MAP decoding [13,34] is a commonly used technique to achieve a higher trellis processing speed. For binary Turbo codes, eg.…”

Section: Qpp Address Generator For Radix-4 Sw-map Decodermentioning

confidence: 99%

“…MAP decoder architectures have been studied by many researchers [24,25,[32][33][34][35]. Several factors, such as interleaver structure and sliding window scheme, must be considered when choosing an appropriate MAP decoder for LTE Turbo decoding.…”

Section: Map Decoder Architecture For Lte Turbo Codesmentioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

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a b s t r a c tWe present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

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High-Throughput Radix-4 logMAP Turbo Decoder Architecture

Cited by 16 publications

References 9 publications

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

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