“…We fabricate four types of offset Corbino TFT with 15 different values of L offset , i.e., 0, 5,10,15,20,25,30,35,40,45,50,55,60,75, 100 µm. The optical images of two fabricated devices are shown in Figure 7.…”
Section: Experimental Verificationmentioning
confidence: 99%
“…While in the field-plate structure, a plate located above the gate edge near the drain offset region is used to suppress the current collapse phenomena by restraining the gate edge electric field concentration [14][15][16][17][18]. Sometimes, these two approaches are used together to increase the breakdown voltage of TFT [19,20].…”
Offset Corbino thin film transistor is a good candidate for high voltage thin film transistor (HVTFT) due to the uniform drain electric field distribution benefiting from the circular structure. The physical model of offset Corbino thin film transistor characteristics has yet to be clarified. In this study, Equations are derived to describe the current–voltage relations of Corbino TFT with offset at the drain or source sides. The influence of offset position and parameters on the saturation voltage and the saturation current was described quantitatively. Three-dimensional Computer-Aided Design simulation and experiment results verify the theoretical physical model. Our physical model provides design rules for high voltage offset Corbino TFT when considering the voltage tolerance and saturation current balance.
“…We fabricate four types of offset Corbino TFT with 15 different values of L offset , i.e., 0, 5,10,15,20,25,30,35,40,45,50,55,60,75, 100 µm. The optical images of two fabricated devices are shown in Figure 7.…”
Section: Experimental Verificationmentioning
confidence: 99%
“…While in the field-plate structure, a plate located above the gate edge near the drain offset region is used to suppress the current collapse phenomena by restraining the gate edge electric field concentration [14][15][16][17][18]. Sometimes, these two approaches are used together to increase the breakdown voltage of TFT [19,20].…”
Offset Corbino thin film transistor is a good candidate for high voltage thin film transistor (HVTFT) due to the uniform drain electric field distribution benefiting from the circular structure. The physical model of offset Corbino thin film transistor characteristics has yet to be clarified. In this study, Equations are derived to describe the current–voltage relations of Corbino TFT with offset at the drain or source sides. The influence of offset position and parameters on the saturation voltage and the saturation current was described quantitatively. Three-dimensional Computer-Aided Design simulation and experiment results verify the theoretical physical model. Our physical model provides design rules for high voltage offset Corbino TFT when considering the voltage tolerance and saturation current balance.
“…HVTFTs are needed in applications such as piezoelectric actuators [1], MEMS [2], xray imaging sensors [3], and soft actuators such as dielectric elastomer actuators [4], where they enable operation at elevated voltages. Recently, amorphous InGaZnO (a-IGZO) TFTs have demonstrated significant potential in high voltage (HV) device applications, owing to their substantial bandgap (>3.1 eV), enabling them to achieve elevated operating voltages [5,6].…”
We report on improved high voltage operation of amorphous-In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) by 
increasing carrier density and distributing the high bias field over the length of the device which utilizes an off-set drain 
structure. By decreasing the O2 partial pressure during sputter deposition of IGZO, the channel carrier density of the high 
voltage a-IGZO TFT (HiVIT) was increased to ~1018 cm-3. Which reduced channel resistance and therefore the voltage drop 
in the ungated offset region during the on-state. To further decrease the electric field in the offset region, we applied Ta 
capping and subsequent oxidation to locally increase the oxygen vacancy levels in the offset region thereby increasing local 
carrier density. The reduction of the drain field in the offset region from 1.90 V/μm to 1.46 V/μm at 200 V drain voltage, 
significantly improved the operational stability of the device by reducing high field degradation. At an extreme drain voltage of 500 V, 
the device showed an off-state current of ~10-11 A and on-state current of ~1.59 mA demonstrating that with further 
enhancements the HiVIT may be applicable to thin-film form, low leakage, high voltage control applications.
“…Among the various high- k dielectrics, Al 2 O 3 has drawn great attention because of its large energy band gap (9 eV), high dielectric breakdown strength (6 MV cm −1 ), high dielectric constant ( k ∼ 9) and good compatibility with oxide semiconductors in TFTs. 27 However, the dielectric properties of Al 2 O 3 gate dielectrics such as the leakage current density and the dielectric constant ( k ) are considerably dependent on the preparation process. Recently, several papers reported on Al 2 O 3 as a gate dielectric obtained by the conventional solution process, where the major challenge to achieve dense films with the desired dielectric properties required high temperature post-deposition treatments (>350 °C).…”
Organic-inorganic (O-I) hybrid materials combine the great variability and interaction at molecular scale demonstrated to impact on properties, especially as gate dielectric thin films in thin-film transistors (TFTs). Benefits such...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.