High-voltage DMOS integrated circuits using floating-gate protection technique

Abstract

An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 lm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.