Detectors and Imaging Devices: Infrared, Focal Plane, Single Photon 2010
DOI: 10.1117/12.860482
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High voltage vs. high integration: a comparison between CMOS technologies for SPAD cameras

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Cited by 9 publications
(7 citation statements)
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“…The CMOS technology offers few possibilities of implementing such guard rings [ 19 , 20 , 21 , 22 ]. By way of example, SPAD, SPAD arrays, and SiPM detection structures with several possible layout techniques for the implementation of guard rings were successfully implemented in 800 nm [ 10 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 ], 700 nm [ 31 ], 500 nm [ 32 , 33 ], 350 nm [ 18 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 ], 180 nm [ 47 , 48 , 49 ], 150 nm [ 50 ], 130 nm [ 15 , 51 , 52 , 53 , 54 , 55 ], and 90 nm [ 56 , 57 ] CMOS nodes, and were used to detect single photon signals on the basis of the avalanche breakdown process. Two main limitations of the CMOS technology remain; namely, the higher dark rate and the lower photon detection efficiency with respect to the custom-technology-based conventional SiPMs.…”
Section: Introductionmentioning
confidence: 99%
“…The CMOS technology offers few possibilities of implementing such guard rings [ 19 , 20 , 21 , 22 ]. By way of example, SPAD, SPAD arrays, and SiPM detection structures with several possible layout techniques for the implementation of guard rings were successfully implemented in 800 nm [ 10 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 ], 700 nm [ 31 ], 500 nm [ 32 , 33 ], 350 nm [ 18 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 ], 180 nm [ 47 , 48 , 49 ], 150 nm [ 50 ], 130 nm [ 15 , 51 , 52 , 53 , 54 , 55 ], and 90 nm [ 56 , 57 ] CMOS nodes, and were used to detect single photon signals on the basis of the avalanche breakdown process. Two main limitations of the CMOS technology remain; namely, the higher dark rate and the lower photon detection efficiency with respect to the custom-technology-based conventional SiPMs.…”
Section: Introductionmentioning
confidence: 99%
“…The trap centers within the forbidden band due to defects and impurities assist the tunneling from the VB to CB, giving the process the name of trap-assisted tunneling. The DCR by tunneling becomes dominant in SPADs fabricated in DSM CMOS technology due to the decreased depletion width and abrupt doping profiles [189]. In order to reduce tunneling, the electric field within the junction should be lowered by decreasing the biasing voltage, but doing so inevitably lowers the PDE as well.…”
Section: Research Challenges and Conclusionmentioning
confidence: 99%
“…Another possibility is offered by the implementation of diffusive lowly doped p guard rings around the p + implantation, as depicted in Figure 7. Such layout was developed using the Teledyne DALSA 800 nm HV, 350 nm HV AMS and Chartered GLOBALFOUNDRIES 130 nm/Tezzaron CMOS technology [18,37,41]. In this case the lowly doped region is smoothing the electric field at the edges of the junction.…”
Section: Sipm In Cmos: Challenges and Limitationsmentioning
confidence: 99%