High-κ gate dielectrics: Current status and materials properties considerations

Wilk, G. D.; Wallace, Robert M.; Anthony, J.

doi:10.1063/1.1361065

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“…These compounds can form in a variety of crystal structures depending on the pressure, temperature, dopant content, and growth conditions, and they have wide applications ranging from superhard protective coatings to catalyst substrates. Furthermore, IVTMO 2 is a suitable replacement for high-performance microelectronic gate dielectrics [6,7].…”

Section: Introductionmentioning

confidence: 99%

Elastic properties, hardness, and anisotropy in baddeleyite IVTMO2 (M=Ti, Zr, Hf)

Chen

Liang

et al. 2015

Sci. China Mater.

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and HfO 2 thin films. Other researchers have investigated the transformation from monoclinic phase to tetragonal phase in HfO 2 [5], as well as its mechanical [11], optical, and elastic properties [12]. Even with this range of study, some properties of IVTMO 2 , particularly their mechanical properties, are not well understood . For example, elastic anisotropy in thin films usually leads to microcracks, and differences in thermal expansion between a film and matrix might induce a dropping of the film from the matrix.Zhao et al. [10] reported that bulk ZrO 2 has three crystalline structures at normal pressure: cubic (2300−2680°C), tetragonal (1170−2300°C), and monoclinic (<1170°C). Bulk HfO 2 has only two crystalline structures: tetragonal (1750−2800°C) and monoclinic (<1750°C). The most abundant polymorph of TiO 2 found in nature is rutile, and at room temperature it is stable up to 12 GPa, where it directly converts to the baddeleyite-type (monoclinic) phase [13]. Because m-HfO 2 has a larger bulk modulus than the other two metal dioxides [12], it was expected to have high hardness. The bulk modulus was once thought to be good predictor of hardness. Although it is true that a hard material must have a high modulus [14], it is a common misconception that an incompressible material is a hard one. For example, osmium has only a twentieth the hardness of diamond, though its bulk modulus is comparable to diamond, making it one of the most incompressible materials known.It is now well recognized that high bulk and shear moduli do not guarantee high hardness. Other factors-including high electron density, short bond length, high degree of covalent bonding, and near-isotropic deformation-usually dominate a material's intrinsic hardness [15]. Thus, it is important to thoroughly investigate baddeleyite-type IVTMO 2 (we henceforth refer to these m-MO 2 materials as m-TiO 2 , m-ZrO 2 , and m-HfO 2 ), especially their hardness, elasticity, and anisotropy. To our best knowledge, there are no systemic studies of monoclinic metal dioxides, which are stable at room temperature. In the past decade,In this article, we used plane-wave density functional theory to investigate the elasticity, anisotropy, and minimum thermal conductivities of baddeleyite type IVTMO2 (m-TiO2, m-ZrO2, and m-HfO2). The elastic constants and modulus, Poisson's ratio, hardness, sound speed, Debye temperature, and minimum thermal conductivities at high temperature were calculated. These calculations show that m-MO2 is not superhard, with a hardness range of about 8-13 GPa. Among these materials, m-TiO2 is the hardest, while m-HfO2 is the least hard. Their elastic and plastic anisotropy are given in detail. Moreover, the m-HfO2 thin film is the most likely to develop microcracks during preparation because it has the highest elastic anisotropy. Among the three dioxides, m-HfO2 is the best thermal barrier because it has the lowest thermal conductivity.

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Section: Introductionmentioning

confidence: 99%

Elastic properties, hardness, and anisotropy in baddeleyite IVTMO2 (M=Ti, Zr, Hf)

Chen

Liang

et al. 2015

Sci. China Mater.

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“…Conduction band offsets with silicon, DE C , and dielectric constant, K, of the high-K gatedielectric materials are taken from Ref. [10] and are presented in Table 1.…”

Section: Resultsmentioning

confidence: 99%

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Hakim

Haque

2004

Solid-State Electronics

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Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region.

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“…[2,3,4]. Thus, the necessity arises to replace the SiO 2 with a dielectric of higher permittivity [5,6]. Application of oxides with a higher dielectric constant (high-k) allows for a physically thicker insulating layer with the same capacitance per unit area as that required for SiO 2 .…”

Section: Fields Of Applicationsmentioning

confidence: 99%

High-K: Latest Developments and Perspectives

Bauer

Lemberger

Erlbacher

et al. 2008

MSF

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Abstract. The paper reviews recent progress and current challenges in implementing high-k dielectrics in microelectronics. Logic devices, non-volatile-memories, DRAMs and low power mixedsignal components are found to be the technologies where high-k dielectrics are implemented or will be introduced soon. Two gate architectures have to be considerd: MOS with metal as gate electrode and MIM. In particular, Hf-silicates for logic and NVM devices in conventional MOS architecture and ZrO 2 for DRAM cells in MIM architecture are discussed. Fields of applicationsThe breakthrough and thus the enormous growth of the microelectronics, especially in the Information Technology, in the past few decades is based, to a large extend, on the SiO 2 /Si system which was therefore called "a simple gift of nature". Gate dielectrics consisting of ultra thin silicon dioxide layers are the key element in conventional silicon based microelectronic devices. In the very beginning of the microelectronics, the thickness of the SiO 2 gate oxide was a few hundred nanometers. Nowadays, state-of-the-art MOSFETs (metal oxide semiconductor field effect transistor) require gate oxide thicknesses of just a few atomic layers. Until recently, the continuous scaling of the ULSI (ultra large scale integration) devices has been accomplished by shrinking physical dimensions. Physical gate oxides with physical thicknesses in the range of 1.6 nm are currently fabricated and thicknesses below 1.0 nm will be requested for future device generations [1]. In this thickness range, key dielectric parameters degrade, like gate leakage current, channel mobility, reliability etc. [2,3,4]. Thus, the necessity arises to replace the SiO 2 with a dielectric of higher permittivity [5,6]. Application of oxides with a higher dielectric constant (high-k) allows for a physically thicker insulating layer with the same capacitance per unit area as that required for SiO 2 . The so-called equivalent oxide thickness (EOT) is defined as follows: EOT = d high-k · k SiO2 / k high-k .(1) d high-k is the physical oxide thickness, k SiO2 and k high-k are the dielectric constant of the silicon dioxide and the high-k oxide, respectively. But, the high-k dielectric has to satisfy several requirements to fulfil all the demands of state-of-the-art gate dielectrics. First, it has to be thermodynamically stable in contact with silicon [7], it must be process compatible with CMOS (complementary MOS) and withstand source/drain implant annealing, oxygen diffusion should be low to prevent generation of a sizeable SiO 2 interface layer (IL) or trapping defects [8], and it must have sufficiently high band offsets to act as barrier for electrons and holes [9]. Also, the high-k oxide has to show a high quality interface to silicon, with only few interface or defect states within the silicon band gap, be- Online: 2008-03-24 ISSN: 1662-9752, Vols. 573-574, pp 165-180 doi:10.4028/www.scientific.net/MSF.573-574.165 © 2008 This is an open access article under the CC-BY 4.0 license (https://creativecomm...

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High-κ gate dielectrics: Current status and materials properties considerations

Cited by 5,793 publications

References 109 publications

Elastic properties, hardness, and anisotropy in baddeleyite IVTMO2 (M=Ti, Zr, Hf)

Elastic properties, hardness, and anisotropy in baddeleyite IVTMO2 (M=Ti, Zr, Hf)

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

High-K: Latest Developments and Perspectives

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