Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing

Chen, W.J.; Shie, Bo-Shiuan; Chin, Albert

doi:10.1109/led.2011.2106478

Cited by 17 publications

(10 citation statements)

References 15 publications

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“…LA also improves the I on / I off ratio and the leakage current of Ge n + p junctions , reaching values of 10 7 and a low leakage current density of 8.3 × 10 −5 A cm −2 . It also allowed the successful fabrication of Ge nMOSFETs, with a ten times better I on / I off performance than for devices with RTA and a peak electron mobility of 603 cm 2 V −1 s −1 .…”

Section: Alternative Implantation Annealing and Doping Schemesmentioning

confidence: 95%

Defect engineering for shallow n‐type junctions in germanium: Facts and fiction

Simoen

Schaekers

Liu

et al. 2016

Physica Status Solidi (a)

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An overview is given on the status of n‐type dopant activation and diffusion in Ge, based on a standard ion implantation and annealing scheme. Emphasis is on defect engineering approaches to optimize either or both parameters. A detailed discussion is given on the use of co‐implantation by neutral or other n‐type dopants. As a case study, the impact of the C ion implantation energy and dose on n‐type junctions in p‐Ge by P + C co‐implantation will be given. It is demonstrated that for fixed P implant conditions, there exist an optimum energy and dose for achieving a minimum junction depth by the formation of C–PV complexes. An alternative approach is the use of self‐interstitial management at the end‐of‐range of the P implantation. Finally, an overview is given of alternatives for obtaining shallow, highly activated n‐type junctions in Ge. They rely on: non‐standard implantation schemes, ultra‐short annealing methods or relying on in situ doped epitaxial deposition.

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Section: Alternative Implantation Annealing and Doping Schemesmentioning

confidence: 95%

Defect engineering for shallow n‐type junctions in germanium: Facts and fiction

Simoen

Schaekers

Liu

et al. 2016

Physica Status Solidi (a)

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“…Moreover, La-based ternary oxides and dual passivation layers have been investigated with good results available, and the characteristics of Ge MOS devices with La-based dielectrics and/or passivation layers reported recently are summarized in Table 5 [56,[127][128][129][130][131][132]. The ZrO 2 /La 2 O 3 dielectric stack has been applied by W. B. Chen et al in Ge n-MOSFET with a laser annealing (LA) treatment to increase its gate capacitance density [133]. The 5-nm high-k IPL and dielectric stack were deposited by PVD, followed by a PDA in O 2 .…”

Section: Ge and Iii-v Metal-oxide-semiconductor (Mos) Devicesmentioning

confidence: 99%

Advances in La-Based High-k Dielectrics for MOS Applications

2019

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This paper reviews the studies on La-based high-k dielectrics for metal-oxide-semiconductor (MOS) applications in recent years. According to the analyses of the physical and chemical characteristics of La2O3, its hygroscopicity and defects (oxygen vacancies, oxygen interstitials, interface states, and grain boundary states) are the main problems for high-performance devices. Reports show that post-deposition treatments (high temperature, laser), nitrogen incorporation and doping by other high-k material are capable of solving these problems. On the other hand, doping La into other high-k oxides can effectively passivate their oxygen vacancies and improve the threshold voltages of relevant MOS devices, thus improving the device performance. Investigations on MOS devices including non-volatile memory, MOS field-effect transistor, thin-film transistor, and novel devices (FinFET and nanowire-based transistor) suggest that La-based high-k dielectrics have high potential to fulfill the high-performance requirements in future MOS applications.

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“…However, Ge nMOSFET suffers from poor device performance due to surface Fermi-level pinning to valance band, low dopant activation, and poor high-κ/Ge interface. To address these issues, novel laser annealing with fast ~30 ns pulse was used [7]- [9]. The laser annealing melts surface semiconductor and re-crystallize within a very short time, which can fully activate the ion-implanted dopants and form ultra-shallow junction.…”

Section: High Mobility Ge Nmosfet For All-ge Cmosmentioning

confidence: 99%

Ge technology beyond Si CMOS

Chin¹

2012

IOP Conf. Ser.: Mater. Sci. Eng.

Self Cite

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To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO 2 /Si value was reached at a medium 0.5 MV/cm effective electric field (E eff) and 1.4 nm equivalent-oxidethickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing E eff , due to the surface Fermi-level pinning to valance band, poor high-κ/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better highfield mobility than universal SiO 2 /Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

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Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing

Cited by 17 publications

References 15 publications

Defect engineering for shallow n‐type junctions in germanium: Facts and fiction

Defect engineering for shallow n‐type junctions in germanium: Facts and fiction

Advances in La-Based High-k Dielectrics for MOS Applications

Ge technology beyond Si CMOS

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