Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Abstract

In this paper, a highly reliable circuit model of gate-all-around (GAA) charge-trap flash (CTF) memory cell is proposed, considering the transient behaviors for describing the program operations with improved accuracy. Although several compact models have been reported in the previous literature, time-dependent behaviors have not been precisely reflected and the failures tend to get worse as the operation time elapses. Furthermore, the developed SPICE models in this work have been verified by the measurement results of the fabricated flash memory cells having silicon–oxide–nitride–oxide–silicon (SONOS). This more realistic model would be beneficial in designing the system architectures and setting up the operation schemes for the leading three-dimensional (3D) stack CTF memory.

A computational study of hafnia-based ferroelectric memories: from ab initio via physical modeling to circuit models of ferroelectric device

“…This parasitic threshold voltage shift is proportional to number of defects filled for certain applied pulse amplitude and length. A straight forward solution to address this parasitic behavior would be to account this shift by an auxiliary subcircuit (see Fig.22a; charge trapping emulation), similar to one reported in [122]. Other implementations like adding a second controlled voltage source in series are possible.…”

Solving Overlapping Pattern Issues in On-Chip Learning of Bio-Inspired Neuromorphic System with Synaptic Transistors

“…The device is potentiated and depressed when holes and electrons are stored in the nitride layer because of the threshold voltage (V T ) change. These weight modulation characteristics of the synaptic transistor are incorporated into a device model with a voltage-controlled current source (VCCS) [30] based on the gate current caused by hot carrier injection [31], as shown in Figure 1b. The VCCS delivers the second gate current (I G2 ) to the nitride layer, which is modeled by the gate current flowing by hot carrier injection as a function of V G2 as per the following equation:…”