Highly efficient CAVLC encoder for MPEG-4 AVC/H.264

Tsai, Tsung‐Han; Chang, Shu-Ping; Fang, Te-Lung

doi:10.1049/iet-cds.2008.0231

Cited by 10 publications

(2 citation statements)

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“…For H.264/AVC, several CAVLC encoder designs have been developed for high performance applications [2][3][4][5][6][7][8][9]. In [4], a highly efficient CAVLC encoder design is developed, and the block-based pipelining scheme is applied to increase encoding efficiency and reduce the pipeline storage elements with the associated input buffer.…”

Section: Introductionmentioning

confidence: 99%

“…In [4], a highly efficient CAVLC encoder design is developed, and the block-based pipelining scheme is applied to increase encoding efficiency and reduce the pipeline storage elements with the associated input buffer. In [6], the proposed CAVLC encoder is based on modification of VLC tables and parallel processing to reduce the hardware size and increase the throughput.…”

Section: Introductionmentioning

confidence: 99%

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A high throughput CAVLC architecture design with two-path parallel coefficients procedure for digital cinema 4K resolution H.264/AVC encoding

Chang

Lin

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a high throughput context-based adaptive variable length code (CAVLC) encoder design with two-path parallel coefficients procedure is developed for H.264/AVC with block based pipelined and parallel processing schemes. By the two-pipe parallel coefficients processing, the proposed block processing based CAVLC encoder only requires 65 encoding cycles/macroblock (MB) on average. Compared with previous encoder designs, the throughput of the proposed architecture is improved over from 23% to 585%. The proposed encoding core modules have smaller area-time (AT) product performance than other designs. By VLSI implementations, the proposed CAVLC encoder can achieve Digital Cinema 4K, i.e. 4096x2160p@37Hz real-time video encoding.

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