Highly Manufacturable Hf-silicate Technology with Optimized Composition for Gate-First Metal Gate CMOSFET

Abstract

Effects of composition in Hf-silicate are evaluated for CMOSFET with TiN gate. Higher k value can be achieved by reducing Si content, effective to improve EOT-Jg performance. Lower Si content is also beneficial in terms of PMOS Vt variation caused by B diffusion. However, enhanced transient charge-trapping effect (TCE) is observed from Hf-silicate with low Si content, degrading electron mobility. Hf-silicate with low Si content also shows more TCE during positive bias stress at low stress bias, which is easily de-trapped. More permanent damage is observed in the Hf-silicate with high Si content due to relatively larger amount of SiO 2 portion in the film. TCE is reduced significantly when Hf-silicate scales aggressively (T physical ≤ 3nm), espcially for low Si content. For high performance application, scaled Hfsilicate with low Si content is desirable due to thinner EOT and less TCE.

Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack

“…B atoms in the dielectric can degrade reliability by producing a charge that shifts V t [9]. However, we have found that B atoms produce a charge only where SiO 2 atoms are present in HfO 2 , i.e., Hf-silicate [10]. The V t shift can be reduced by using the lowest optimal SiO 2 concentration in the HfSiO dielectric, even though more B diffusion might occur.…”