2011 3rd IEEE International Memory Workshop (IMW) 2011
DOI: 10.1109/imw.2011.5873213
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Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications

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Cited by 12 publications
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“…With our nanocrystal memory, a large window over 3 V is achievable. Not only are program speed and nanocrystal capacity sufficient to obtain a large shift in programmed V t distribution, but the process is controlled and gives tight distributions important for ensuring consistent product results [23]. Figure 10 shows erased V t distributions of single arrays with increasing bitcell density from 1 to 32 Mb.…”
Section: Bitcell Operationmentioning
confidence: 99%
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“…With our nanocrystal memory, a large window over 3 V is achievable. Not only are program speed and nanocrystal capacity sufficient to obtain a large shift in programmed V t distribution, but the process is controlled and gives tight distributions important for ensuring consistent product results [23]. Figure 10 shows erased V t distributions of single arrays with increasing bitcell density from 1 to 32 Mb.…”
Section: Bitcell Operationmentioning
confidence: 99%
“…2, is required to provide the best electrical memory performance and reliability [22]. Freescale has developed an enhanced coverage process (ECP) to control both nanocrystal size and density [23], which is used to improve charge capacity and the charge capturability of the nanocrystal layer. With the ECP process, area coverage is increased from $30% for the prior baseline process to $60%, at some expense to nanocrystal size uniformity and sphericity.…”
mentioning
confidence: 99%
“…Basically, a NCM cell consists of a metal-oxide-semiconductor field effect transistor (MOSFET) with mono-disperse nanometerscale crystals embedded within the gate dielectric and associates the finite-size effects of NCs and the benefits (robustness and fault-tolerance) of a stored charge distribution. The last few years, significant advances have been made in NC fabrication (see, e.g., [2,3]) and prototype NCM-based products for low-power microcontroller applications have recently been demonstrated [4]. However, the NCM technologies developed to date still face the concern of producing high-density of uniformly distributed size-homogeneous NCs and hence, cannot avoid fluctuations in device performance and fail to exploit size-dependence effects [2,[5][6][7][8].…”
Section: Introductionmentioning
confidence: 99%
“…In order to reduce the operating voltages, the integration of high-k materials in the gate stack was also proposed [4,5]. Other architectures like split-gate memories [6,7] allow reducing the energy consumption of the memory, but require the addition of a select transistor, controlling the programming current.…”
Section: Introductionmentioning
confidence: 99%