Highly Reconfigurable Logic‐In‐Memory Operations in Tunable Gaussian Transistors for Multifunctional Image Processing

Abstract

Reconfigurable logic‐in‐memory device, albeit a promising hardware platform for constructing parallel computing architectures, still suffers from high power‐consumption and low area‐efficiency arising from the circuit redundancy in silicon (Si) based technical path. 2D materials are identified as potential building blocks to significantly reduce the circuit footprints with outstanding power‐efficiency, owing to their atomically thin nature and unique electronic properties. However, the present 2D logic devices are primarily based on single channel materials with homogeneous transport polarities, limiting the device reconfigurability for multi‐functional applications. Here, 2D p–n junction based dual‐gate Gaussian‐type transistors for simplified reconfigurable logic circuits are reported. All fundamental Boolean logic operators are implemented in a single device with electrically driven reconfigurability, giving rise to an ultra‐low transistor consumption down to 13% of the traditional circuits. The device is also demonstrated as a reliable image processing unit for various computing tasks (pixel processing, comparing, and ciphering) by executing the corresponding logic operations. Moreover, in situ memory of the Boolean logics is achieved by engineering the dielectric properties of the transistor without compromising its reconfigurability. These findings provide a potential approach to achieving reconfigurable logic‐in‐memory operations at the hardware level, with significant implications for the advancement of parallel computing.

Multifunctional In-Memory Logics Based on a Dual-Gate Antiambipolar Transistor toward Non-von Neumann Computing Architecture

“…These were selected as the n-type and p-type semiconductors and the gate insulator, respectively. The 2D materials have advantages as regards producing the AAT because the 2D materials have surfaces that are atomically flat and free of dangling bonds. , The van der Waals stacking thus makes it possible to form an ideal p–n heterojunction regardless of the lattice mismatch. ,, As a result, large peak-to-valley ratios (PVRs) of 10 3 –10 5 have been achieved in 2D material-based AATs. − These advantages have enabled the development of multivalued logic circuits , and two-input logic circuits. − Another important constituent of our device is polystyrene with a zinc phthalocyanine core (ZnPc-PS 4 ), which works as a nanofloating gate. This material has a three-dimensional (3D) structure where a ZnPc core (semiconductor) is surrounded by four polystyrene chains (insulator) to form a star-shaped polymer. − Hence, carriers can be stably stored in the ZnPc core to provide a nonvolatile memory function.…”