Highly Reliable Flash Cell for Low Power Application

Abstract

The electrical properties of a split-gate-type flash cell are investigated and optimized by junction engineering to obtain a high reliability. Phosphorus implantation is conducted to form a cell source junction, and the following three different anneal conditions change voltage coupling ratio between the source and the floating gate. As the ratio increases, it is observed that program characteristic is improved and endurance property is degraded, which matches well with simulation result. Therefore, cells in the pure N2 group are considered to be optimized cells. Optimized cells guarantee 105 cycle endurance, and show excellent program disturbance and bake retention properties.

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

“…Split-gate flash memory has been widely studied for embedded memory applications thanks to its high programming efficiency, low power consumption and immunity to over-erase problem. [1][2][3][4][5][6][7][8][9][10][11] Source-side injection (SSI) of hot electrons is most commonly utilized to program the cell because both high lateral and vertical field are obtained in the gap region with proper bias. 1) The charge-storage layer of split-gate memory can be floating poly, nitride 9) or nanocrystal.…”