Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive &amp;amp; Smartcard Applications

Shum, D.; Power, J. R.; Ullmann, R.; Suryaputra, E.; Ho, Kin‐Yip; Hsiao, Ju-Hung; Tan, Charles; Langheinrich, W.; Bukethal, Christoph; Pissors, V.; Tempel, G.; Rohrich, M.; Gratz, Achim; Iserhagen, A.; Andersen, Eli; Paprotta, S.; Dickenscheid, W.; Strenz, R.; Duschl, R.; Kern, Thomas; Hsieh, Cheng-Hsiang; Huang, C.M.; Ho, Chia-Tong; Kuo, H.H.; Hung, Chih-Chien; Lin, Yuh-Chieh; Tran, L.C.

doi:10.1109/imw.2012.6213670

Cited by 15 publications

(6 citation statements)

References 7 publications

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“…As a first case consider a system similar to the one modeled in [6] where in (8) and ( 9) we have n 512, f s 360 Hz and b x 11; the compression stage refers to (10) and for the dispatch stage with b y 11 we consider (12) where data are stored in a FLASH memory [22]. The overall power consumption W is…”

Section: Dispatch Stagementioning

confidence: 99%

See 1 more Smart Citation

Rakeness-Based Design of Low-Complexity Compressed Sensing

Mangia

Pareschi

Cambareri³

et al. 2017

IEEE Trans. Circuits Syst. I

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Compressed Sensing (CS) can be introduced in the processing chain of a sensor node as a mean to globally reduce its operating cost, while maximizing the quality of the acquired signal. We exploit CS as a simple early-digital compression stage that performs a multiplication of the signal by a matrix. The operating costs (e.g., the consumed power) of such an encoding stage depend on the number of rows of the matrix, but also on the value and position of the rows' coefficients. Our novel design flow yields optimized sparse matrices with very few rows. It is a non-trivial extension of the rakeness-based approach to CS and yields an extremely lightweight stage implemented by a very small number of possibly signed sums with an excellent compression performance. By means of a general signal model we explore different corners of the design space and show that, for example, our method is capable of compressing the signal by a factor larger than 2.5 while not considering 30% of the original samples (so that they may not be acquired at all, leaving the analog front-end and ADC stages inactive) and by processing each of the considered samples with not more than three signed sums

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Section: Dispatch Stagementioning

confidence: 99%

“…Then, define few convex subsets of the space of n ¢ n matrices, namely C PSD containing matrices satisfying ( 5) and ( 6), C Ave containing matrices satisfying (5) as well as ( 16), C Ter containing matrices satisfying ( 5) and ( 17), and C Loc containing matrices satisfying (5) and (22).…”

Section: A Solving T-rltmentioning

confidence: 99%

Rakeness-Based Design of Low-Complexity Compressed Sensing

Mangia

Pareschi

Cambareri³

et al. 2017

IEEE Trans. Circuits Syst. I

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“…Simple comparison with respect to erasecoupling-ratio among several NVM cells is shown. New 1.5T-flash (type-C) shows high erase coupling ratio than other types (type-A, type-B) [1,4,5]. Poly-to-poly erase operation in type-C decouples unselected cells, resulting in immunity to disturbance contrary to bulk erase operation in type-A and type-B.…”

Section: Electrical Results and Discussionmentioning

confidence: 99%

A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance

Lee

Seo

et al. 2014

2014 IEEE 6th International Memory Workshop (IMW)

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For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triplegate flash architecture, high speed operation (write time of 25us and erase operation of less than 2ms) and robust reliability (1M cycle, 150 retention) are achieved.

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“…4 (2015) angle structure around a source contact that is not conductive optically. [33][34][35] Accordingly, a self-aligned contact (SAC) technology has been introduced to enable a NOR cell at approximately 45 nm. [33] The SAC architecture can further scale down the NOR cell by introducing patterning-friendly line/space features rather than 1D holes to form drain plugs, and by allowing the direct proximity of drain plugs over the gate spacer.…”

Section: Physical Scaling Challengingmentioning

confidence: 99%

Physical principles and current status of emerging non-volatile solid state memories

Wang

Yang

Wen

2015

Electron. Mater. Lett.

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Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for the next generation of data-storage devices based on a comparison of their performance.

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Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive & Smartcard Applications

Cited by 15 publications

References 7 publications

Rakeness-Based Design of Low-Complexity Compressed Sensing

Rakeness-Based Design of Low-Complexity Compressed Sensing

A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance

Physical principles and current status of emerging non-volatile solid state memories

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