Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link

Abstract

SUMMARYThis paper presents highly reliable multiple-valued onephase signalling for an asynchronous on-chip communication link under process, supply-voltage and temperature variations. New multiple-valued dual-rail encoding, where each code is represented by the minimum set of three values, makes it possible to perform asynchronous communication between modules with just two wires. Since an appropriate current level is individually assigned to the logic value, a sufficient dynamic range between adjacent current signals can be maintained in the proposed multiple-valued current-mode (MVCM) circuit, which improves the robustness against the process variation. Moreover, as the supply-voltage and the temperature variations in smaller dimensions of circuit elements are dominated as the common-mode variation, a local reference voltage signal according to the variations can be adaptively generated to compensate characteristic change of the MVCM-circuit component. As a result, the proposed asynchronous on-chip communication link is correctly operated in the operation range from 1.1 V to 1.4 V of the supply voltage and that from −50 • C to 75 • C under the process variation of 3σ. In fact, it is demonstrated by HSPICE simulation in a 0.13-μm CMOS process that the throughput of the proposed circuit is enhanced to 435% in comparison with that of the conventional 4-phase asynchronous communication circuit under a comparable energy dissipation.

Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links

“…To realize high-throughput asynchronous data-communication links, it is desirable to eliminate the spacer codewords [18], [19]. In this subsection, two-color open-fault resilient codes are defined and its fault detectability is proven.…”

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

“…They operate as a large NoC that contains several tens of processing cores and more in a chip. Each NoC includes processing cores with asynchronous on-chip network, which consists of switching routers and on-chip data-transmission links [15], [16] designed using asynchronous circuits. Each processing core transmits/receives packets, which basically include header, body, and tail flits [2], [3].…”