Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects

Abstract

Multilevel metal interconnects are crucial for the development of large-scale organic integrated circuits. In particular, three-dimensional integrated circuits require a large number of vertical interconnects between layers. Here, we present a novel multilevel metal interconnect scheme that involves solvent-free patterning of insulator layers to form an interconnecting area that ensures a reliable electrical connection between two metals in different layers. Using a highly reliable interconnect method, the highest stacked organic transistors to date, a three-dimensional organic integrated circuits consisting of 5 transistors and 20 metal layers, is successfully fabricated in a solvent-free manner. All transistors exhibit outstanding device characteristics, including a high on/off current ratio of ~10 7 , no hysteresis behavior, and excellent device-to-device uniformity. We also demonstrate two vertically-stacked complementary inverter circuits that use transistors on 4 different floors. All circuits show superb inverter characteristics with a 100% output voltage swing and gain up to 35 V per V.

Nanoscale control by chemically vapour-deposited polymers

“…The ultrasmooth, ultrathin (3-15 nm), flexible, and crosslinked organosilicon layer, poly(2,4,6trivinyl-2,4,6-trimethyl cyclotrisiloxane) (PV3D3, dielectric constant, k~2.2), has been integrated into devices 80,81 , including 3D stacking of organic thin film transistors (TFTs) 82 . The PV3D3 serves as an electret layer when coupled with an ultrathin (20 nm) crosslinked iCVD poly(1,4butanediol diacrylate) (PBDDA) film as blocking dielectric (Fig.…”

Vertically Integrated Electronics: New Opportunities from Emerging Materials and Devices

“…In the solvent-based printing method, only dielectric materials that are soluble to the solvent can be used, which can limit the material selection. Alternatively, a via-hole-less multi-metal interconnection strategy was proposed by dielectric patterning [ 39 ]. A solvent-free deposition method for polymer dielectrics, called initiated chemical vapor deposition (iCVD), was utilized to achieve the robust insulating properties even with the ultrathin dielectric thickness [ 40 – 42 ].…”

“…Utilizing this all-dry method and shadow mask patterning, the polymer dielectric layer was directly patterned during the deposition process, which allows for the vertical interconnection without via-hole formation. The vertically stacked inverter circuits were fabricated by using transistors on 4 different floors verifying the reliable metal interconnection through this method [ 39 ]. Unlike planar structures, metal interconnections between different layers are critical for the vertically integrated devices.…”

Hybrid Thin-Film Materials Combinations for Complementary Integration Circuit Implementation

“…Their three-dimensional (3D) stacked structure can minimize the physical distance and increase the drivability of the electronic circuits by resolving the interconnection lengths and parasitic resistances [118,119]. However, the fabrication process of the vertically stacked inverter is highly complicated and difficult [120,121]. In 2010, Nomura et al fabricated vertically stacked n-type IGZO transistors and p-type poly-(9,9-dioctylfluorene-co-bithiophene) (F8T2) thin film transistors on a flexible PET substrate as shown in Figure 7a,b [122].…”