Highly vectorizable fault simulation on the Cray X-MP supercomputer

Parallel and Vector Logic and Fault Simulation Algorithms on the Cray Y-MP Supercomputer

“…The maximum speedup was 6 for the 8-CPU batch environment. The performance is measured by Mp [7], the number of gate-fault evaluations per second, calculated as where zu is the word lengtll in bits, N~is the number of (effective) gates in the circuit, P is the number of simulator passes, v is the number of input patterns (constant of 512 in this research) simulated, and T is the total fault simulation time in seconds.…”

“…Speedups in Table 1 are calculated from: 3. Parallel-and-Vector Fault Simulation Algorithm 3.1 Algorithm Description A gate-level, two-valued, zero-delay highly vectorizable parallel fault simulation (HVPFS) algorithm for combinational circuits, described in [7] was designed to take advantage of the vector processing capabilities of a single processor in the Cray X-MP/28. Here, we present an implementation of the parallel fault simulation method that combines vectorization and multiprocessing.…”

“…The parallel fault simulation method, on the other hand, involves Boolean operations on all gates in the circuit, for all input test patterns and all single faults, that can be parallelized and vectorized with a constant vector length. A vector version of the algorithm is described in [7] where each gate evaluation operation is performed for all input test patterns and is thus vectorized. In Section 3, a parallel-and-vector fault simulation algorithm is presented where parallelization is achieved by performing independent gate evaluations concurrently on different processors.…”