Histogram Computation with a Reconfigurable Memory Based Fast VLSI Architecture

Abstract

Computation of histogram is the primary work that used in digital image processing systems. Mutual Information is the best measurement that also used for image registration. Calculation of the mutual information requires obtaining separate and combining histogram of the two images. By the increase of the histogram size, the demand for the hardware resource for the computation of the histogram is increased. This paper about the computation of the memory-based VLSI architecture has been shown. The architecture of the computation of the histogram is existed by using the plotting in the field programmable field array. Parallelization of histogram functions is a major problem due to memory collisions. So, to avoid these collisions there is a new technique called parallel histogram computation used. To implement the parallel histogram, it is requiring dual–ported memory. By making the computation of the histogram fast, there are several benefits obtained. Some of the examples are texture classification, image compression, etc shown in this manuscript.