HITEC: a test generation package for sequential circuits

Niermann, T.M.; Patel, J.H.

doi:10.1109/edac.1991.206393

Cited by 499 publications

(177 citation statements)

References 19 publications

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“…The experiments were run on a Pentium Mobile, with 2.0 GHz processor and 1GB DDR2 RAM. We have used test sets generated by HITEC [19], which achieve full coverage of all detectable faults in the circuits. HITEC test sets are used for comparison with the work in [1,2,12].…”

Section: Resultsmentioning

confidence: 99%

Efficient test compaction for combinational circuits based on Fault detection count-directed clustering

Khursheed

2007

IET Comput. Digit. Tech.

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Test compaction is an effective technique for reducing test data volume and test application time. In this paper, we present a new static test compaction technique based on test vector decomposition and clustering. Test vectors are decomposed and clustered for faults in an increasing order of faults detection count. This clustering order gives more degree of freedom and results in better compaction. Experimental results demonstrate the effectiveness of the proposed approach in achieving higher compaction in a much more efficient CPU time than previous clustering-based test compaction approaches.

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Section: Resultsmentioning

confidence: 99%

Efficient test compaction for combinational circuits based on Fault detection count-directed clustering

Khursheed

2007

IET Comput. Digit. Tech.

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“…The steps of this process require first identifying a minimal set of test vectors whose application will reveal a near-total percentage of possible faults [3] [4] [5]. Second, the desired tests are applied by shifting test stimuli into the circuit using an industry standard (JTAG) interface [6].…”

Section: Introductionmentioning

confidence: 99%

Output compression for IC fault detection using compressive sensing

Tarsa

Kung

2012

MILCOM 2012 - 2012 IEEE Military Communications Conference

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Abstract-The process of detecting logical faults in integrated circuits (ICs) due to manufacturing variations is bottlenecked by the I/O cost of scanning in test vectors and offloading test results. Traditionally, the output bottleneck is alleviated by reducing the number of bits in output responses using XOR networks, or computing signatures from the responses of multiple tests. However, these many-to-one computations reduce test time at the cost of higher detection failure rates, and lower test granularity. In this paper, we propose an output compression approach that uses compressive sensing to exploit the redundancy of correlated outputs from closely related tests, and of correlated faulty responses across many circuits. Compressive sensing's simple encoding method makes our approach attractive because it can be implemented on-chip using only a small number of accumulators. Through simulation, we show that our method can reduce the output I/O bottleneck without increasing failure rates, and can reconstruct higher granularity results off-chip than current compaction approaches.

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“…A node u is said to be a (structural) single-vertex dominator of another node v if every path from v to a primary output passes through u. Single-vertex dominators can be found in linear-time [9,45] and have been used for optimizing various CAD tasks, e.g., test pattern generation [64,89]. More recently, they have been leveraged in the gate-level debugger in [110], which performs an initial debugging pass on selected dominator gates.…”

Section: Introductionmentioning

confidence: 99%

Formal Methods in Computer-Aided Design

Srivas¹,

Camilleri²

1996

Lecture Notes in Computer Science

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The third contribution aims to advance the state-of-the-art of QBF solvers, whose progress has not been as impressive as that of SAT solvers. We present a framework for using complete dominators to preprocess and reduce QBFs with an inherent circuit structure, which is comii mon in encodings of PSPACE-complete CAD problems. Experiments show that three modern QBF solvers together solve 55% of preprocessed QBF instances, compared to none without preprocessing.The final contribution consists of a series of QBF encodings for evaluating the reconfigurability of partially programmable circuits (PPCs). The metrics of fault tolerance, design error tolerance and engineering change coverage are defined for PPCs and encoded using QBFs.These formulations along with experimental results demonstrate the theoretical and practical appropriateness of QBFs for dealing with reconfigurability.iii

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HITEC: a test generation package for sequential circuits

Cited by 499 publications

References 19 publications

Efficient test compaction for combinational circuits based on Fault detection count-directed clustering

Efficient test compaction for combinational circuits based on Fault detection count-directed clustering

Output compression for IC fault detection using compressive sensing

Formal Methods in Computer-Aided Design

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