HLS-based sensitivity-inductive soft error mitigation for satellite communication systems

Chen, Xiang; Yang, Wenhui; Zhao, Ming; Wang, Jing

doi:10.1109/iolts.2016.7604688

Cited by 2 publications

(1 citation statement)

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“…Other work has notably used HLS to apply reliability through other means than replication. For example, Chen et al [19] introduce an HLS approach that uses both TMR and gate-level hardening technique called gate sizing on different resources to minimize both soft error rate and area overhead. In another example, Hammouda et al [20] propose a design flow that automatically generates on-chip monitors to enable runtime checking of control flow and I/O timing behavior errors in HLS hardware accelerators.…”

Section: Related Workmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.

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Section: Related Workmentioning

confidence: 99%