Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

Hayashi, Mariko; Sometani, Mitsuru; Hatakeyama, Tatsuko; Yano, Hiroshi; Harada, Shinsuke

doi:10.7567/jjap.57.04fr15

Cited by 10 publications

(17 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many studies reported on the Vth instability upon negative gate bias stress on MOSFETs [9, 52,70]. However, to get insights on the basic trapping mechanisms of NIOTs in the insulator, it is useful to analyse the behaviour of p-type MOS capacitors ( Figure 11) [71]. Figure 11 shows a comparison of different techniques to determine the shift ΔVth in MOSFETs (current measurements) and the flat band voltage shift ΔVFB in MOS capacitors (capacitance measurements).…”

Section: Charge Trapping Phenomenamentioning

confidence: 99%

See 1 more Smart Citation

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

2019

View full text Add to dashboard Cite

This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

show abstract

Section: Charge Trapping Phenomenamentioning

confidence: 99%

“…∆V FB (equivalent to ∆V th ) as a function of the stress time measured with different electrical characterization techniques. Data taken from Reference[71].…”

mentioning

confidence: 99%

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

2019

View full text Add to dashboard Cite

show abstract

“…16,17) On the other hand, NO-POA degrades the threshold voltage stability through enhanced hole trapping. [18][19][20] We previously reported that N atoms are preferentially introduced into the SiC side of the SiO 2 /SiC interface in the initial stage of NO-POA; then, they are distributed on the SiO 2 side as nitridation proceeds. 21,22) Considering that SiN film is used as a charge-trapping layer in current nonvolatile memory devices, 23) we expect that the threshold voltage stability could be improved by selectively removing N atoms distributed on the SiO 2 side.…”

mentioning

confidence: 99%

Impact of post-nitridation annealing in CO₂ ambient on threshold voltage stability in 4H-SiC metal-oxide-semiconductor field-effect transistors

Hosoi

Ohsako

Moges

et al. 2022

Appl. Phys. Express

Self Cite

View full text Add to dashboard Cite

The combination of NO annealing and subsequent post-nitridation annealing (PNA) in CO2 ambient for SiO2/SiC structures has been demonstrated to be effective in obtaining both high channel mobility and superior threshold voltage stability in SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs). N atoms on the SiO2 side of the SiO2/SiC interface incorporated by NO annealing, which are plausible cause of charge trapping sites, could be selectively removed by CO2-PNA at 1300°C without oxidizing the SiC. CO2-PNA was also effective in compensating oxygen vacancies in SiO2, resulting high immunity against both positive and negative bias-temperature stresses.

show abstract

“…Besides the initial performance of SiC-MOS devices, long-term reliability related to for example, the threshold voltage (V th ) shift due to carrier trapping near the SiO 2 =SiC interfaces, is a crucial issue. Although the advantages and drawbacks of interface nitridation were previously reported, 27,28) details about the relationship between the interface structure and electrical properties have not been explored yet.…”

mentioning

confidence: 99%

“…Actually, in addition to the mobility degradation, the harmful impact of NO-POA on the long-term reliability of SiC-MOSFETs on Si-face substrates has been reported. 27,28) Although the as-oxidized device without NO-POA showed a significant V th shift even for a short stress time and a rapid V th shift was proven to be suppressed by NO-POA, the long-term V th reliability of the NO-treated device severely deteriorated with increasing stress time. Considering the correlation between these reports and the nitrogen depth profiles shown in Fig.…”

mentioning

confidence: 99%

Sub-nanometer-scale depth profiling of nitrogen atoms in SiO₂/4H-SiC structures treated with NO annealing

Moges

Sometani

Hosoi

et al. 2018

Appl. Phys. Express

View full text Add to dashboard Cite

We developed a technique to probe, with sub-nanometer-scale resolution, depth profiles of nitrogen atoms in NO-treated SiO2/4H-SiC structures for Si- and C-face substrates. This technique revealed that preferential nitridation only at the SiO2/SiC interfaces proceeds in the initial stage of NO annealing. Then, for the Si-face, a longer NO treatment leads to a nitrogen distribution in SiO2 within a few nm of the interface. This result is in line with the mobility degradation in MOSFETs subjected to excessive NO annealing. For the C-face, a larger amount of nitrogen was introduced and the depth profile was unchanged after reaching a saturation level.

show abstract

Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

Cited by 10 publications

References 33 publications

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Impact of post-nitridation annealing in CO₂ ambient on threshold voltage stability in 4H-SiC metal-oxide-semiconductor field-effect transistors

Sub-nanometer-scale depth profiling of nitrogen atoms in SiO₂/4H-SiC structures treated with NO annealing

Contact Info

Product

Resources

About

Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

Cited by 10 publications

References 33 publications

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Impact of post-nitridation annealing in CO2 ambient on threshold voltage stability in 4H-SiC metal-oxide-semiconductor field-effect transistors

Sub-nanometer-scale depth profiling of nitrogen atoms in SiO2/4H-SiC structures treated with NO annealing

Contact Info

Product

Resources

About

Impact of post-nitridation annealing in CO₂ ambient on threshold voltage stability in 4H-SiC metal-oxide-semiconductor field-effect transistors

Sub-nanometer-scale depth profiling of nitrogen atoms in SiO₂/4H-SiC structures treated with NO annealing