Holistic comparison of optical routers for chip multiprocessors

Abstract

Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multiprocessors (CMPs). However, traditional NoCs using metallic interconnects consume a significant amount of power to deliver high communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and optical routers, and promise significant bandwidth and power advantages. In this work, we review different designs of 5x5 and 4x4 optical routers for mesh or torus-based optical NoCs, and compare them for cost of optical resources and optical power loss. Besides, we use a 8x8 mesh-based optical NoC as a case study and analyze the thermal-induced power overhead while using different optical routers. Results show that the number of switching stages in an optical link directly affects the total optical power loss under thermal variations. By using passive-routing optical routers, the maximum number of switching stages in a XY-routing path is minimized to three, and the thermal-induced power overhead in the optical NoC is less than the matched networks using other routers.Index Terms-Chip multiprocessor, optical network-on-chip, optical router.

Universal method for constructing N-port non-blocking optical router based on 2 × 2 optical switch for photonic networks-on-chip

“…In this paper, we propose a universal method for constructing the N-port non-blocking optical router, in which all MR optical switches or M-Z optical switches behave as 2 × 2 optical switches. The optical router constructed by this method has minimum optical switches, in which the number of the optical switch is reduced about 50% compared to the reported optical routers based on MR optical switches [25][26][27][28][29][30][31][32] and more than 30% compared to the reported optical routers based on M-Z optical switches [24], and therefore is more compact in footprint and more power-efficient. By using passive-routing optical links [21], we can further reduce the power consumption of the optical router.…”

“…Any N-port non-blocking optical router for photonic NoC must obey the following rules, which have been adopted in the reported optical routers [19][20][21][22][23][24][25][26][27]:…”

“…Many topologies for photonic NoCs have been widely studied, such as Mesh [19], Cluster-Mesh, Torus [20], Crossbar [21], Fat-Tree [22] and Clos [23]. [24][25][26][27][28][29][30][31][32][33][34][35][36][37]. Only 4-and 5-port optical routers are not enough to construct all photonic NoCs.…”

“…Although MR optical switch or M-Z optical switch can manipulate two optical links simultaneously, most reported optical routers fully utilize them as 1 × 2 optical switches [25][26][27][28][29][30][31][32] or partly utilize them as 1 × 2 optical switches [24]. In this paper, we propose a universal method for constructing the N-port non-blocking optical router, in which all MR optical switches or M-Z optical switches behave as 2 × 2 optical switches.…”

Power and Signal-to-Noise Ratio Optimization in Mesh-Based Hybrid Optical Network-on-Chip Using Semiconductor Optical Amplifiers

“…When the waveguide crossing loss is -0.12 dB, the insertion loss of the input/output port in the 5 × 5 Crux router is shown in Table 2. The crux router is the optimized optical router for the insertion loss and the SNR when using X-Y routing [25]. A shown Table 2, the optical router has different insertion loss values depending on the signal flow at the input/output ports.…”