HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era

Afsharmazayejani, Raheel; Yazdanpanah, Fahimeh; Rezaei, Amin; Alaei, Mohammad; Daneshtalab, Masoud

doi:10.1007/978-3-319-78890-6_25

Applied Reconfigurable Computing. Architectures, Tools, and Applications

2018

DOI: 10.1007/978-3-319-78890-6_25

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HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era

Raheel Afsharmazayejani

Fahimeh Yazdanpanah

Amin Rezaei

et al.

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Cited by 7 publications

References 31 publications

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A Survey on Heterogeneous CPU–GPU Architectures and Simulators

Alaei,

Yazdanpanah

2024

Concurrency and Computation

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Heterogeneous architectures are vastly used in various high performance computing systems from IoT‐based embedded architectures to edge and cloud systems. Although heterogeneous architectures with cooperation of CPUs and GPUs and unified address space are increasingly used, there are still a lot of open questions and challenges regarding the design of these architectures. For evaluation, validation and exploration of next generation of heterogeneous CPU–GPU architectures, it is essential to use unified heterogeneous simulators for analyzing the execution of CPU–GPU workloads. This article presents a systematic review on challenges of heterogeneous CPU–GPU architectures with covering a diverse set of literatures on each challenge. The main considered challenges are shared resource management, network interconnections, task scheduling, energy consumption, and programming model. In addition, in this article, the state‐of‐the‐art of heterogeneous CPU–GPU simulation platforms is reviewed. The structure and characteristics of five cycle‐accurate heterogeneous CPU–GPU simulators are described and compared. We perform comprehensive discussions on the methodologies and challenges of designing high performance heterogeneous architectures. Moreover, for developing efficient heterogeneous CPU–GPU simulators, some recommendations are presented.

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A Survey on Heterogeneous CPU–GPU Architectures and Simulators

Alaei,

Yazdanpanah

2024

Concurrency and Computation

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RETRACTED: Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

Singh

Ravindra²,

Naik

2022

Trans Emerging Tel Tech

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Nowadays, network‐on‐chip (NoC) routers become important in several applications including mobile technology and digital communication. Multiple cores/processors are typically coupled using NoC routers, which considerably improve integrated circuit performance in terms of power, latency, throughput, and area. So, a novel 4 × 4 topology‐based NoC router using multi‐priority based iterative round‐robin matching with slip (MPiSLIP) routing algorithm is implemented in this work. The proposed work contains different operational blocks classification such as route computation using static straight allocator, route controlling using MPiSLIP arbiter, a crossbar switch, combined parallel virtual channel and switch allocation unit, look ahead bypass route computation (LBRC), and input‐output ports. The MPiSLIP routing mechanism also determines the priorities necessary for route development. Finally, by bypassing the switches and fulfilling all of the priories in a look‐ahead manner, LBRC is employed to establish the effective path between input ports and output ports. The simulation results show that the proposed MPiSLIP‐based NoC routing method resulted in a reduced area, power, and latency as compared to the open‐source NoCs, multi‐processor NoCs, multi‐core NoCs, and conventional routing algorithms.

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An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip

et al. 2018

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HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era

Cited by 7 publications

References 31 publications

A Survey on Heterogeneous CPU–GPU Architectures and Simulators

A Survey on Heterogeneous CPU–GPU Architectures and Simulators

RETRACTED: Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip

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