Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

“…Other studies have applied schedulability analysis to NoCs that use dynamic arbiters. For instance, in [18], the authors used static analysis to estimate the worst-case communication latency in an NoC that uses a Hop-based arbiter. This approach uses a weighted graph to identify the traffic flow that causes the worst latency.…”

“…Schedulability Analysis for [14] computer systems [12] real-time system using NoC with fixed-priority arbitration [15] real-time system using NoC with fixed-priority arbitration (extended to include self-blocking contention) [16] real-time system using NoC with fixed-priority arbitration (considering end-to-end latency and task dependencies) [17] real-time system using NoC with fixed-priority arbitration (reducing pessimism by analyzing traffic flow interference in sections of respective paths) [18] real-time system using NoC with Hop-based arbiter [19] real-time system using NoC with Earliest-Deadline-First policy and wormhole switching [20] real-time system using NoC with round-robin arbitration and multiple stages [21] best-effort NoC with round-robin arbitration and multiple stages [22] 2D mesh NoC with round-robin arbiter and two routing algorithms [23] NoC with round-robin arbiter (considering worst-case scenarios, unblocking delay, and influence of indirect flows)…”

“…Metric Main features and error in relation to simulation [15] maximum latency static arbitration, did not consider buffers in the model, and did not present the average error in the text. [17] maximum latency did not consider the depth of buffers in the model and did not present the error in relation to simulation, only the improvement of the analysis compared to a previous work [18] worst-case inter-core communication latency static arbitration, only evaluated in the direct blocking model and did not consider the buffer size, error less than 10% [20] worst-case end-to-end latencies simulated a specific scenario with only three flows, did not consider buffer size, static arbitration, analysis error varied from 32% to 11% [21] maximum latency did not consider the buffer size and did not reported the error because the simulator was not able to reach the worst case [22] maximum latency only made the comparison of routing algorithms and did not show the error in relation to simulation [23] maximum latency reduced the error by 11.38% for packets with 2 flits and by 1.27% for packets with 19 flits real-time systems to evaluate the schedulability of tasks with temporal requirements. The WCA can provide a preliminary evaluation of task mappings, avoiding unnecessary simulations of non-schedulable configurations and, consequently, a reduction in the exploration time of the design space.…”