Hot-Carrier Injection Degradation in Advanced CMOS Nodes: A Bottom-Up Approach to Circuit and System Reliability

Huard, V.; Cacho, F.; Federspiel, X.; Mora, P.

doi:10.1007/978-3-319-08994-2_14

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…The 3dimensional density of state is proportional to the energy, the energy distribution of electrons at room temperature (300K) is plotted in Fig. 6a, which shows that majority of the electrons are at low energy in meV range, whereas the center energy of even the lowest energy of the trap is in order of several kT (∼ 0.026eV ) [44]. This means that only a small fraction of electrons at the tail of the distribution could participate in the de-trapping process.…”

Section: Frequency Dependence Of Wearout and Recoverymentioning

confidence: 99%

Implications of accelerated self-healing as a key design knob for cross-layer resilience

Guo

Stan

2017

Integration

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In this paper we propose a cross-layer accelerated self-healing (CLASH) system which "repairs" its wearout issues in a physical sense through accelerated and active recovery, by which wearout can be reversed while actively applying several accelerated self-healing techniques, such as high temperature and negative voltages. Different from previous solutions of coping with wearout issues (e.g. BTI) by "tolerating", "slowing down" or "compensating", which still leave the irreversible (permanent) wearout component unchecked, the proposed solution is able to fully avoid the irreversible wearout through periodic rejuvenation, and this is inspired by the explored frequency dependent behaviors of wearout and (accelerated and active) recovery based on measurements on FPGAs. We demonstrate a case where the chip can always be brought back to the fresh status by employing a pattern of 31-hour regular operation (under room temperature and nominal voltage) followed by a 1-hour accelerated selfhealing (under high temperature and negative voltage). The proposed system integrates the notions of accelerated self-healing across multiple layers of the system stack. At the circuit level, a negative voltage generator and heating elements are designed and implemented; at the architecture level, the core can be allocated in a way such that the dark silicon or redundant resources can be healed by active elements; at the system level, right balance of stress and accelerated/active recovery can be employed by the system scheduler to fully mitigate the wearout; various wearout sensors act as the media between different layers. Overall, these techniques work together to guarantee that the whole system performs for more of the time at higher levels of performance and power efficiency by fully taking advantage of the extra opportunities enabled by the accelerated self-healing.

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Section: Frequency Dependence Of Wearout and Recoverymentioning

confidence: 99%

Implications of accelerated self-healing as a key design knob for cross-layer resilience

Guo

Stan

2017

Integration

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“…Defect energies are discussed in the chapter of Aichinger [11], with the subsequent temperature accelerated recovery in the chapter of Pobegen [12]. The chapters of Huard [6], Scholten [13], and Schlünder [14] discuss bridging the gap between device and circuit models. Hot carrier damage in various device types (LDMOS, FinFET, SiGe BJTs, and SiGe channel PFETs) is discussed in the chapters of Reggiani [15], Alagi [16], Cho [17], Chakraborty [18], and Franco [19].…”

Section: Introductionmentioning

confidence: 99%

“…This book addresses in detail the various aspects necessary in a first principles model and the steps that various groups have taken to use such models in real life circuit lifetime prediction. The chapters of Bravaix [5], Huard [6], and Tyaginov [7] attempt to provide predictive models from the underlying physics. Some characteristics of hot electron distributions and how to approximate them are described in the chapters of Rauch [8], Bina [9], Zaka [10], and Tyaginov [7].…”

Section: Introductionmentioning

confidence: 99%