How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs

Zhou, Catherine L.; Tang, Wai-Chung; Lo, Wing-Hang; Wu, Yu-Liang

doi:10.1109/dac.2007.375296

Cited by 3 publications

(2 citation statements)

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“…This technique has been widely applied for many EDA optimization problems, such as circuit optimization [1]- [6], partitioning [7] and FPGA synthesis [8] [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Improving redundancy addition and removal using unreachable states for sequential circuits

Yang

Xiao

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Redundancy Addition and Removal (RAR), one of the major combinational logic perturbation techniques, has been shown to be very useful for many EDA optimization tasks. However, all the currently known RAR techniques did not analyze and make use of unreachable states, which are abundant in sequential circuits. These unreachable states can be considered as input don't cares and can add an extra flexibility in locating alternative wires. In this paper, we study the fundamental theory and propose a reasoning scheme for locating alternative wires without performing wasteful redundancy tests. To explore the deeper effect of unreachable states, the concept is extended to illegal assignments and the fault independent redundancy identification is applied on illegal assignments to find flexibilities introduced by unreachable states. On the experiments carried for both MCNC and industry benchmarks, it is shown that using such an idea, a remarkable increase of more than 100% (averagely) in the number of alternative wires can be found, which should be quite useful as most of today's practical circuits are sequential.

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“…This technique has been widely applied for many EDA optimization problems, such as circuit optimization [1]- [6], partitioning [7] and FPGA synthesis [8] [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Improving redundancy addition and removal using unreachable states for sequential circuits

Yang

Xiao

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…Rewiring is a technique to transform the logic of input circuits without affecting their overall functionalities. Indeed, rewiring has been proven to be a powerful tool for optimization in many different EDA fields [1][2][3][4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques

Chim

Lam

et al. 2011

IEICE Trans. Fundamentals

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The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods. It has been proven that rewiring is able to further improve some already excellent results on many EDA problems, ranging from logic minimization, partitioning, FPGA technology mappings to final routings. Previous studies have shown that ATPG-based rewiring is one of the most powerful tools for logic perturbation while a graph-based rewiring engine is able to cover nearly one fifth of the target wires with 50 times runtime speedup. For some problems that only require good-enough and very quick solutions, this new rewiring technique may serve as a useful and more practical alternative. In this work, essential elements in graph-based rewiring such as rewiring patterns, pattern size and locality, etc., have been studied to understand their relationship with rewiring performance. A structural analysis on the target-alternative wire pairs discovered by ATPG-based and graphbased engines has also been conducted to analyze the structural characteristics that favor the identification of alternative wires. We have also developed a hybrid rewiring approach that can take the advantages from both ATPG-based and graph-based rewiring. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wire coverage when compared with the state-of-the-art ATPGbased rewiring engine with only 4% of the runtime. Through applying our hybrid rewiring approach to the FGPA technology mapping problem, we could achieve similar depth level and look-up table number reductions with much shorter runtime. This shows that the fast runtime of our hybrid approach does not sacrifice the quality of certain rewiring applications.

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2016

Boolean Circuit Rewiring

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How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs

Cited by 3 publications

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Improving redundancy addition and removal using unreachable states for sequential circuits

Improving redundancy addition and removal using unreachable states for sequential circuits

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques

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