How Not to Protect Your IP – An Industry-Wide Break of IEEE 1735 Implementations

Speith, Julian; Schweins, Florian; Ender, Maik; Fyrbiak, Marc; May, Alexander; Paar, Christof

doi:10.1109/sp46214.2022.9833605

Cited by 6 publications

(4 citation statements)

References 23 publications

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“…While the concept of standards appears to have many benefits, standardization processes can often be lengthy and require a great deal of resource commitment (e. g., time, expertise, willingness to compromise) from all involved stakeholders. It is possible that standards will end up at the lowest common denominator of industry and policymakers, will not be properly executed or even be flawed [24,95], or in the worst case, contain maliciously built-in backdoors [23].…”

Section: Standardsmentioning

confidence: 99%

Expanding Explainability: From Explainable Artificial Intelligence to Explainable Hardware

Speith¹,

Speith²,

Becker³

et al. 2023

Preprint

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The increasing opaqueness of Artificial Intelligence (AI) and its growing influence on our digital society highlight the necessity for AI-based systems that are trustworthy, accountable, and fair. Previous research emphasizes explainability as a means to achieve these properties. In this paper, we argue that system explainability cannot be achieved without accounting for the underlying hardware on which all digital systems-including AI applications-are realized. As a remedy, we propose the concept of explainable hardware, and focus on chips-which are particularly relevant to current geopolitical discussions on (trustworthy) semiconductors. Inspired by previous work on Explainable AI (XAI), we develop a hardware explainability framework by identifying relevant stakeholders, unifying existing approaches form hardware manufacturing under the notion of explainability, and discussing their usefulness to satisfy different stakeholders' needs. Our work lays the foundation for future work and structured debates on explainable hardware. CCS Concepts: • Hardware → Integrated circuits; • Security and privacy → Human and societal aspects of security and privacy; • Computing methodologies → Philosophical/theoretical foundations of artificial intelligence.

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Section: Standardsmentioning

confidence: 99%

Expanding Explainability: From Explainable Artificial Intelligence to Explainable Hardware

Speith¹,

Speith²,

Becker³

et al. 2023

Preprint

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show abstract

“…Code encryption is a method of converting code into ciphertext by using a key, and is preferred to prevent intellectual property leakage through key management. Nevertheless, due to the necessity of compliance with the regulations of the Institute of Electrical and Electronics Engineers (IEEE) [4], the encryption can only rely on the key of the electronic design automation (EDA) software company. This arrangement introduces a potential vulnerability, as there exists a risk of information disclosure from the EDA software company endowed with key management responsibilities.…”

Section: Introductionmentioning

confidence: 99%

“…hide all the parameters with important information and add false parameters in the code to heighten the complexity of analysis; (3). insert a strong covert module in critical paths to extend the critical paths to achieve the purpose of destroying the synthesized effect of the circuit; (4). split all the "aggregate" sentences to increase the code while ensuring that the functions of the obfuscated code are consistent with the source code.…”

Section: Introductionmentioning

confidence: 99%

Optimizing RTL Code Obfuscation: New Methods Based on XML Syntax Tree

Yi,

Zhang,

Liu

2023

Applied Sciences

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As the most widely used description code in digital circuits and system on chip (SoC), the security of register transfer level (RTL) code is extremely critical. Code obfuscation is a typical method to ensure the security of RTL code, but popular obfuscation methods are not fully applicable to RTL code. In addition, some RTL code obfuscation tools also have issues with incomplete functionality or obfuscation errors. In view of the above issues, this paper studies the RTL code security problem represented by obfuscation. Based on the extensible markup language (XML) syntax tree generated by parsing RTL code, a complete RTL code refactoring model is constructed, and four targeted RTL code obfuscation methods are proposed, namely: Layout obfuscation; Parameter obfuscation; Critical path obfuscation; Code increment obfuscation. Utilizing the developed obfuscation tool, an assessment of the performance and effectiveness of the obfuscation methods is conducted, alongside testing the equivalence between the obfuscated code and the source code. The experimental results show that the proposed obfuscation methods have higher practicability and reliability, and have the characteristics of high obfuscation coverage that can be stable at over 98% and preservation of compiler indicative Comments.

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“…Unfortunately, it was demonstrated that this standard suffers from side-channel leakage by EDA tools, and accordingly, to the disclosure and undetectable tampering of the IPs [3,20]. In addition, the private keys relied upon by the standard may be stolen directly from the EDA tool source code/binaries, as recently demonstrated in [29]. Such attacks highlight the importance of EDA tools in protecting the confidentiality of IPs.…”

Section: Introductionmentioning

confidence: 99%

Garbled EDA: Privacy Preserving Electronic Design Automation

Hashemi¹,

Roy²,

Ganji³

et al. 2022

Preprint

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The complexity of modern integrated circuits (ICs) necessitates collaboration between multiple distrusting parties, including thirdparty intellectual property (3PIP) vendors, design houses, CAD/EDA tool vendors, and foundries, which jeopardizes confidentiality and integrity of each party's IP. IP protection standards and the existing techniques proposed by researchers are ad hoc and vulnerable to numerous structural, functional, and/or side-channel attacks. Our framework, Garbled EDA, proposes an alternative direction through formulating the problem in a secure multi-party computation setting, where the privacy of IPs, CAD tools, and process design kits (PDKs) is maintained. As a proof-of-concept, Garbled EDA is evaluated in the context of simulation, where multiple IP description formats (Verilog, C, S) are supported. Our results demonstrate a reasonable logical-resource cost and negligible memory overhead. To further reduce the overhead, we present another efficient implementation methodology, feasible when the resource utilization is a bottleneck, but the communication between two parties is not restricted. Interestingly, this implementation is private and secure even in the presence of malicious adversaries attempting to, e.g., gain access to PDKs or in-house IPs of the CAD tool providers. CCS CONCEPTS• Security and privacy → Tamper-proof and tamper-resistant designs; Hardware attacks and countermeasures;

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How Not to Protect Your IP – An Industry-Wide Break of IEEE 1735 Implementations

Cited by 6 publications

References 23 publications

Expanding Explainability: From Explainable Artificial Intelligence to Explainable Hardware

Expanding Explainability: From Explainable Artificial Intelligence to Explainable Hardware

Optimizing RTL Code Obfuscation: New Methods Based on XML Syntax Tree

Garbled EDA: Privacy Preserving Electronic Design Automation

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