How to simulate 1000 cores

Monchiero, Matteo; Ahn, Jung Ho; Falcón, Ayose; Ortega, Daniel; Faraboschi, Paolo

doi:10.1145/1577129.1577133

Cited by 55 publications

(21 citation statements)

References 23 publications

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“…This is due to excessive synchronisation in the benchmarks beyond 64 cores, and the fact that our simulator can execute tight spin-lock loops at near native speed. It is a well-known fact that the SPLASH-2 benchmarks attract high synchronisation costs for large-scale hardware configurations, as shown by other research [12]. The MULTIBENCH results are not affected in the same way due to less synchronisation.…”

Section: E Scalabilitymentioning

confidence: 61%

Scalable multi-core simulation using parallel dynamic binary translation

Almer

Böhm

Koch

et al. 2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (ISS) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (JIT) dynamic binary translation (DBT). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (ISA). We have evaluated our parallel simulation methodology against the industry standard SPLASH-2 and EEMBC MULTIBENCH benchmarks and demonstrate simulation speeds up to 25,307 MIPS on a 32-core x86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead.

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Section: E Scalabilitymentioning

confidence: 61%

Scalable multi-core simulation using parallel dynamic binary translation

Almer

Böhm

Koch

et al. 2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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“…We employ the GEMS simulator [26] fed with memory accesses generated by PIN [25] as explained by Monchiero et al [27]. The interconnection network has been modeled with GARNET [5], included in the GEMS toolset.…”

Section: Simulation Methodologymentioning

confidence: 99%

Automatic detection of extended data-race-free regions

Jimborean

Waern

Ekemark

et al. 2017

2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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Data-race-free (DRF) parallel programming becomes a standard as newly adopted memory models of mainstream programming languages such as C++ or Java impose data-racefreedom as a requirement.We propose compiler techniques that automatically delineate extended data-race-free regions (xDRF), namely regions of code which provide the same guarantees as the synchronization-free regions (in the context of DRF codes). xDRF regions stretch across synchronization boundaries, function calls and loop back-edges and preserve the data-racefree semantics, thus increasing the optimization opportunities exposed to the compiler and to the underlying architecture. Our compiler techniques precisely analyze the threads' memory accessing behavior and data sharing in shared-memory, general-purpose parallel applications and can therefore infer the limits of xDRF code regions.We evaluate the potential of our technique by employing the xDRF region classification in a state-of-the-art, dualmode cache coherence protocol. Larger xDRF regions reduce the coherence bookkeeping and enable optimizations for performance (6.8%) and energy efficiency (11.7%) compared to a standard directory-based coherence protocol.

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“…To model many-core multiprocessors, we take an approach similar to [9,20] of building a hierarchical framework where cycle-accurate simulations of individual cores are combined by a top-level chip-wide simulator to model an entire many-core processor. Our framework is illustrated in Figure 5.…”

Section: Evaluation Methodology 41 Simulation Infrastructurementioning

confidence: 99%

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Winter

Albonesi

Shoemaker

2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

124

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Future many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hardware imperfections, the runtime thread scheduler and global power manager must be nimble enough to handle such random heterogeneity. With hundreds of cores expected on a single die in the future, these algorithms must provide high power-performance efficiency, yet remain scalable with low runtime overhead.This paper presents a range of scheduling and power management algorithms and performs a detailed evaluation of their effectiveness and scalability on heterogeneous many-core architectures with up to 256 cores. We also conduct a limit study on the potential benefits of coordinating scheduling and power management and demonstrate that coordination yields little benefit. We highlight the scalability limitations of previously proposed thread scheduling algorithms that were designed for small-scale chip multiprocessors and propose a Hierarchical Hungarian Scheduling Algorithm that dramatically reduces the scheduling overhead without loss of accuracy. Finally, we show that the high computational requirements of prior global power management algorithms based on linear programming make them infeasible for many-core chips, and that an algorithm that we call Steepest Drop achieves orders of magnitude lower execution time without sacrificing power-performance efficiency.

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How to simulate 1000 cores

Cited by 55 publications

References 23 publications

Scalable multi-core simulation using parallel dynamic binary translation

Scalable multi-core simulation using parallel dynamic binary translation

Automatic detection of extended data-race-free regions

Scalable thread scheduling and global power management for heterogeneous many-core architectures

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