HPC Accelerators with 3D Memory

Abstract

Abstract-After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have conquered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. This year, major vendors have introduced new accelerators based on 3D memory, like Xeon Phi Knights Landing by Intel and Pascal architecture by Nvidia. This paper reviews hardware features of those new HPC accelerators and unveils potential performance for scientific applications, with an emphasis on Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) used by commercial products according to roadmaps already announced.

A Case For Intra-rack Resource Disaggregation in HPC

“…Future high performance computing (HPC) systems are expected to have a variety of compute and memory resources as a means to reduce cost and preserve performance scaling [78]. The onset of this trend is evident in recent HPC systems that feature partially-programmable compute accelerators, with graphical processing units (GPUs) quickly gaining traction [62,77].…”

“…Future high performance computing (HPC) systems are driven towards heterogeneity of compute and memory resources in response to the expected halt of traditional technology scaling, combined with continuous demands for increased performance [56,78] and the wide landscape of HPC applications [69]. In the long term, many HPC systems are expected to feature a variety of graphical processing units (GPUs), partially-programmable accelerators [62,77], ixed-function accelerators [11,61,68], reconigurable accelerators such as ield programmable gate arrays (FPGAs) [40,70], and new classes of memory [80] that blur the line between memory and storage technology.…”