Hthreads: A Computational Model for Reconfigurable Devices

Peck, W.; Anderson, E.; Agron, Jason; Stevens, Jim; Baijot, Fabrice; Andrews, Davıd L.

doi:10.1109/fpl.2006.311336

Cited by 53 publications

(37 citation statements)

References 4 publications

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“…1145/2815631 CPUs and FPGA cores. Projects such as Hthreads [Peck et al 2006], HybridOS [Kelm and Lumetta 2008], and BORPH [Brodersen et al 2006] all address this problem. However, these solutions utilize custom operating system kernels and often only support CPUs running on the FPGA fabric.…”

Section: Introductionmentioning

confidence: 99%

RIFFA 2.0: A reusable integration framework for FPGA accelerators

Jacobsen

Kastner

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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We present RIFFA 2.1, a reusable integration framework for Field-Programmable Gate Array (FPGA) accelerators. RIFFA provides communication and synchronization for FPGA accelerated applications using simple interfaces for hardware and software. Our goal is to expand the use of FPGAs as an acceleration platform by releasing, as open source, a framework that easily integrates software running on commodity CPUs with FPGA cores. RIFFA uses PCI Express (PCIe) links to connect FPGAs to a CPU's system bus. RIFFA 2.1 supports FPGAs from Xilinx and Altera, Linux and Windows operating systems, and allows multiple FPGAs to connect to a single host PC system. It has software bindings for C/C++, Java, Python, and Matlab. Tests show that data transfers between hardware and software can reach 97% of the achievable PCIe link bandwidth.

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Section: Introductionmentioning

confidence: 99%

RIFFA 2.0: A reusable integration framework for FPGA accelerators

Jacobsen

Kastner

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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“…The Hthreads project [23,2] has developed both hardware and software infrastructures for the deployment of hybrid HW-SW FPGA systems. Their approach is similar to our work in the sense that it is based on a shared memory model using a system bus; both SW and HW tasks execute according to a multitasking model.…”

Section: Related Workmentioning

confidence: 99%

Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems

Pellizzoni

Caccamo

2008

2008 IEEE Real-Time and Embedded Technology and Applications Symposium

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“…In our work, no OS is required and the thread support is completely integrated into the HLS tool itself, permitting auto-generation of a complete system, synthesizeable by commercial RTL synthesis tools. HybridThreads (hthreads) is a real-time embedded operating system which allows programmers to run threads simultaneously on a CPU and on an FPGA [15,9,10]. The authors provide an hthreads API, which, while similar to the Pthreads API, is nonetheless a non-standard approach to parallelization.…”

Section: Introductionmentioning

confidence: 99%

From software threads to parallel hardware in high-level synthesis for FPGAs

Choi

Brown

Anderson

2013

2013 International Conference on Field-Programmable Technology (FPT)

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Abstract-We describe the support within high-level hardware synthesis (HLS) for two standard software parallelization paradigms: Pthreads and OpenMP. Parallel code segments, as specified in the software, are automatically synthesized by our HLS tool into parallel-operating hardware sub-circuits. Both data parallelism and task-level parallelism are supported, as is the combined use of both Pthreads and OpenMP. Moreover, our work also provides automated synthesis for commonly occurring synchronization constructs within the Pthreads/OpenMP library: mutual exclusion (mutex) and barriers. Essentially, our framework allows a software engineer to specify parallelism to an HLS tool using methodologies they are likely to be familiar with. An experimental study considers a variety of parallelization scenarios, including demonstrated speedups of up to 12.9 in circuit wall-clock time for the 16-thread case and area-delay product as low as 12% ( 8 improvement) when using 4 pipelined hardware threads.

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Hthreads: A Computational Model for Reconfigurable Devices

Cited by 53 publications

References 4 publications

RIFFA 2.0: A reusable integration framework for FPGA accelerators

RIFFA 2.0: A reusable integration framework for FPGA accelerators

Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems

From software threads to parallel hardware in high-level synthesis for FPGAs

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