Human and Robotic Space Mission Use Cases for High-Performance Spaceflight Computing

Some, Raphael; Doyle, Richard J.; Bergman, L.; Whitaker, William; Powell, Wesley; Johnson, Michael; Goforth, Montgomery B.; Lowry, Michael

doi:10.2514/6.2013-4729

Cited by 5 publications

(7 citation statements)

References 5 publications

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“…For example, Eqs. (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15) demonstrate the process of calculating device metrics for Freescale QorIQ ® P5040, which is a quadcore CPU [21][22][23]. CD calculations require information about the operating frequency, the number of each type of computational unit, and the number of operations per cycle that can be achieved by each type of computational unit for all operations mixes and data types considered.…”

Section: Device Metrics Methodologymentioning

confidence: 99%

“…Although current space-grade processors increasingly lag behind the capabilities of emerging COTS processors [1][2][3], computing requirements for space missions are becoming more demanding due to the increasing need for real-time sensor and autonomous processing [4][5][6]. Furthermore, improving sensor technology and increasing mission data rates, data precisions, and problem sizes are increasing the demand for communication bandwidth to ground stations.…”

Section: Introductionmentioning

confidence: 99%

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Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

Lovelly

George

2017

Journal of Aerospace Information Systems

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Due to harsh and inaccessible operating environments, space computing presents many unique challenges and constraints that limit onboard computing performance. However, the increasing need for real-time sensor and autonomous processing, coupled with limited communication bandwidth with ground stations, is increasing onboard computing demands for next-generation space missions. Because currently available space-grade processors cannot satisfy this growing demand, research into various processors is conducted to ensure that potential new processors are based upon architectures that will best meet the computing needs of space missions. Device metrics are used to measure and compare the theoretical capabilities of processors based upon vendor-provided data and tools, enabling the study of large and diverse sets of architectures. Architectural tradeoffs are determined that can be considered when comparing or designing space-grade processors. Results demonstrate how onboard computing capabilities are increasing due to emerging architectures that support high levels of parallelism in terms of computational units, internal memories, and input/output resources; and that performance varies between applications, depending on the compute-intensive kernels used. Furthermore, the overheads incurred by radiation hardening are quantified and used to analyze low-power commercial-off-the-shelf processors for potential hardening and use in future space missions.

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Section: Device Metrics Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

Lovelly

George

2017

Journal of Aerospace Information Systems

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“…Local response normalization (LRN) is a technique mainly used during deep learning training to improve accuracy, presented in 2012 by AlexNet [24]; its purpose is to perform local normalization on convolution values, and the specific calculation method can be found in Equation (3). LRN mimics the activity of biological neurons by creating a competitive mechanism, introducing competition between feature maps generated by adjacent convolution kernels.…”

Section: Local Response Normalization Benchmarkmentioning

confidence: 99%

“…In recent years, with the increasing demand for space exploration, future space science missions will use larger sensors, higher sampling frequencies, and more accurate instruments compared to those in existing space science missions. Tasks such as autonomous exploration of robots and active debris removal require highly autonomous operations, which require more powerful on-board processing capabilities [1][2][3][4]. Traditional processors used for space missions cannot meet these high-performance requirements, and the process of redeveloping, producing, and certifying space-grade processors is lengthy, complex, and costly.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation Method for Intelligent Computing Components for Space Applications

Xie,

Wang,

et al. 2023

Sensors

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The computational performance requirements of space payloads are constantly increasing, and the redevelopment of space-grade processors requires a significant amount of time and is costly. This study investigates performance evaluation benchmarks for processors designed for various application scenarios. It also constructs benchmark modules and typical space application benchmarks specifically tailored for the space domain. Furthermore, the study systematically evaluates and analyzes the performance of NVIDIA Jetson AGX Xavier platform and Loongson platforms to identify processors that are suitable for space missions. The experimental results of the evaluation demonstrate that Jetson AGX Xavier performs exceptionally well and consumes less power during dense computations. The Loongson platform can achieve 80% of Xavier’s performance in certain parallel optimized computations, surpassing Xavier’s performance at the expense of higher power consumption.

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“…There is a need of using more powerful devices, in terms of computing power, while keeping reliability, low power, weight and cost. Space agencies have been developing, during the last years, projects for designing new devices to fulfil this gap, as the High Performance Spaceflight Computing (HPSC) Processor initiative of NASA [1], or to test the feasibility of using modern commercial off-the-shelf components (COTS) devices in the space environment, as is the case of the HiRel program from ESA [2].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics

Pérez

Otero

Torre

2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Zynq UltraScale+ (ZU+) devices contain a variety of computing fabrics of different nature and purpose to support complex adaptive heterogeneous system applications with active fault tolerance techniques. Namely, the Processor Management Unit (PMU) and the R5 processors are candidates for hosting the scrubbing and reconfiguration tasks, as well as for dealing with other fault detection and repair tasks originated in, for instance, Triple-Modular Redundancy (TMR) structures in the reconfigurable logic section. This paper contains a performance and trade-off analysis of different scrubbing techniques (ECCbased and readback) when handled by different components such as the Soft-Error Mitigation IP (SEM-IP), the Real Time Processing Unit (RPU) processors or the Platform Management Unit (PMU) processor. The implementation of the measured strategies has been selected in order to be compatible with dynamic and partial reconfiguration functions in order to also have higher additivity at HW level.

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Human and Robotic Space Mission Use Cases for High-Performance Spaceflight Computing

Cited by 5 publications

References 5 publications

Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

Performance Evaluation Method for Intelligent Computing Components for Space Applications

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics

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