HW/SW Co-design of the Instrument Control Unit for the Energetic Particle Detector on-board Solar Orbiter

Sánchez, S. F.; Prieto, Manuel; Polo, Óscar R.; Parra, Pilar; Silva, Antonio da; Gutiérrez, O.; Castillo, Ronald; Fernández, José Martínez; Rodrı́guez-Pacheco, J.

doi:10.1016/j.asr.2013.05.029

Cited by 12 publications

(4 citation statements)

References 15 publications

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“…The BSW is a criticality category B software, which cannot be replaced during mission, with minimal functionality comprising only the system start-up and the safe mode. This software was developed by our research group, and more details of its design can be found in [57]. Although the BSW is a much more significant example of a real embedded system than quicksort or RVS tutorial example, its size, which exceeds 32 KiB in its instrumented version, is too long to be executed in the current version of RV32Xtrace, which has no more than 4KiB memory.…”

Section: Results Analysismentioning

confidence: 99%

A RISC-V Processor Design for Transparent Tracing

et al. 2020

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Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code determines where to insert the tracing instructions, so that later, the execution time can be captured using a logic analyser. The main drawback of this technique is the overhead introduced by the execution of trace instructions. This paper proposes a modification of the architecture of a RISC pipelined processor that eliminates the execution time overhead introduced by the code instrumentation. In this way, it allows the tracing to be non-intrusive, since the sequence and execution times of the program under analysis are not modified by the introduction of traces. As a use case of the proposed solution, a processor, based on RISC-V architecture, was implemented using VHDL language. The processor, synthesized on a FPGA, was used to execute and evaluate a set of examples of instrumented code generated by a “worst-case execution time” estimation tool. The results validate that the proposed architecture executes the instrumented code without overhead.

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Section: Results Analysismentioning

confidence: 99%

A RISC-V Processor Design for Transparent Tracing

et al. 2020

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“…In order to fix this problem, some research makes use of several hardware or software configuration files. One acts as a baseline that is not allowed to be modified, while others act as updates [22][23][24]. A controller switches among them.…”

Section: Of 13mentioning

confidence: 99%

Remote System Update for System on Programmable Chip Based on Controller Area Network

et al. 2017

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Abstract:In some application domains, using a download cable to update the system on a programmable chip (SoPC) is infeasible, which reduces the maintainability and flexibility of the system. Hence the remote system update (RSU) scheme is being studied. In this scheme, the serial configuration (EPCS) device involves a factory mode configuration image, which acts as the baseline, and an application mode configuration image, which is used for some specific functions. Specifically, a new application mode image is delivered through the controller area network (CAN) with the improved application layer protocol. Besides, the data flow and data check for transmitting a new image are constructed to combine the transmission reliability with efficiency. The boot sequence copying hardware configuration code and software configuration code is analyzed, and the advanced boot loader is carried out to specify boot address of the application mode image manually. Experiments have demonstrated the feasibility of updating and running a new application mode image, as well as rolling back into the factory mode image when no application mode image is available. This scheme applies a single CAN bus, which makes the system easy to construct and suitable for the field distributed control system.

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“…Furthermore, even if the hardware was already available, this virtual platform offers, not possible otherwise, nonintrusive and exhaustive debug and fault injection capabilities. The overall ICU hardware/software codesign is described in [6].…”

Section: Problem Statement and Related Workmentioning

confidence: 99%

Runtime Instrumentation of SystemC/TLM2 Interfaces for Fault Tolerance Requirements Verification in Software Cosimulation

Silva

Parra

Polo

et al. 2014

Modelling and Simulation in Engineering

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This paper presents the design of a SystemC transaction level modelling wrapping library that can be used for the assertion of system properties, protocol compliance, or fault injection. The library uses C++ virtual table hooks as a dynamic binary instrumentation technique to inline wrappers in the TLM2 transaction path. This technique can be applied after the elaboration phase and needs neither source code modifications nor recompilation of the top level SystemC modules. The proposed technique has been successfully applied to the robustness verification of the on-board boot software of the Instrument Control Unit of the Solar Orbiter’s Energetic Particle Detector.

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HW/SW Co-design of the Instrument Control Unit for the Energetic Particle Detector on-board Solar Orbiter

Cited by 12 publications

References 15 publications

A RISC-V Processor Design for Transparent Tracing

A RISC-V Processor Design for Transparent Tracing

Remote System Update for System on Programmable Chip Based on Controller Area Network

Runtime Instrumentation of SystemC/TLM2 Interfaces for Fault Tolerance Requirements Verification in Software Cosimulation

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