HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs

Joven, Jaume; Strict, Per; Castells-Rufas, David; Bagdia, Akash; Micheli, Giovanni De; Carrabina, Jordi

doi:10.1109/sies.2011.5953649

Cited by 7 publications

(11 citation statements)

References 3 publications

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“…Examples include ARM Cortex-M1, Freescale ColdFire V1, or MIPS Technologies MP32. For instance, in [27] an ARM Cortex-M1 hard processor was implemented in both Xilinx and Altera FPGAs to provide designs with an IEEE 754-compatible floating point unit.…”

Section: A Ip Coresmentioning

confidence: 99%

Advanced Features and Industrial Applications of FPGAs—A Review

Rodríguez-Andina

Valdes-Pena

Moure

2015

IEEE Trans. Ind. Inf.

147

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research interests include the design of SoC systems based on FPGA, focusing on signal acquisition and conditioning, signal processing, and wireless sensors networks for industrial applications.María J. Moure (M'99) is an Associate Professor at the Department of Electronic Technology, University of Vigo. Her research interests include the design of SoC systems based on FPGA, focusing on signal acquisition and conditioning, signal processing, and wireless sensors networks for industrial applications.

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Section: A Ip Coresmentioning

confidence: 99%

Advanced Features and Industrial Applications of FPGAs—A Review

Rodríguez-Andina

Valdes-Pena

Moure

2015

IEEE Trans. Ind. Inf.

147

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“…It can be used in all embedded systems fields (image processing, aerospace systems, security and industrial applications, etc.). It can be implemented on different architectures (hardware, software or both hardware/software) using different design methodologies (Joven et al 2011) as illustrated on Fig. 1.…”

Section: Design Implementation Architecturesmentioning

confidence: 99%

“…The choice of hardware/software partitioning, using co-design approach, presents a trade-off among various design metrics such as performance, cost, flexibility and time-to-market (López-Vallejo and López 2003;Joven et al 2011). Several approaches of hardware/software partitioning are presented.…”

Section: System Level Specificationmentioning

confidence: 99%

Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances

Mhadhbi

Litayem

Othman

et al. 2014

Complex System Modelling and Control Through Intelligent Soft Computations

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Due to their flexible architecture, lower-cost and faster processing, Field Programmable Gate Array (FPGA) presents one of the stimulating choices for implementing modern embedded systems. This is due to their intrinsic parallelism, fast processing speed, rising integration scale and lower-cost solution. This kind of platforms can be considered as a futuristic implementation platform. The growing configurable logic capacity of FPGA has enabled designers to incorporate one or more processors in FPGA platform. In contrast to the traditional hard cores, the soft cores processors present an interesting solutions for implementing embedded applications. They give designers the ability to adapt many configurations to their specific application; including memory subsystems, interrupt handling, ISA features, etc. Faced to the various problems related to the selection of an efficient soft-core FPGA embedded processor with appropriate configuration, co-design methodology presents a good deal for embedded designers. The most crucial step in the design of embedded systems is the hardware/software partitioning. This step consists of deciding which component is suitable for hardware implementation and which one is more appropriate for software implementation. This research field is especially active (always on the move) and several approaches are proposed. In this chapter, we will present our contribution on the hardware/software partitioning co-design approach, and discuss their involvement on design acceleration and architecture performances. The first part of this chapter describes the effect of the MicroBlaze Xilinx configuration on the embedded system performance. The second part

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“…As presented in [42], the system can optionally integrate an AHB-based decoupled Floating Point Unit (FPU) to support hardware-assisted floating point operations. In our case, the FPU must be connected through an AMBA AHB Network Interface (NI) instead of being connected directly to an AHB matrix.…”

Section: Overview Of the Proposed Clustered Noc-based Mpsoc Platmentioning

confidence: 99%

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Joven

Bagdia

Angiolini³

et al. 2013

IEEE Trans. Ind. Inf.

Self Cite

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Abstract-Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the overall system performance may be affected due to congestion, and therefore parallel programming stacks must be assisted by quality-of-service (QoS) support to meet application requirements and to deal with application dynamism.In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform.The experimental results show the efficiency of our software stack under a broad range of parallel kernels and benchmarks, in terms of low-latency interprocess communication, good application scalability, and most important, they demonstrate the ability to enable runtime reconfiguration to manage workloads in message-passing parallel applications.Index Terms-Networks-on-chip (NoCs), NoC-based multiprocessor systems-on-chip (MPSoC), parallel computing, quality of service (QoS), runtime reconfiguration.

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HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs

Abstract: Abstract-Nowadays

Cited by 7 publications

References 3 publications

Advanced Features and Industrial Applications of FPGAs—A Review

Advanced Features and Industrial Applications of FPGAs—A Review

Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

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