HW/SW Implementation of Hyperspectral Target Detection Algorithm

A reconfigurable multi-mode implementation of hyperspectral target detection algorithms

“…The FPGA-based ACE detection accelerator in [7] can be used for subsequent runs of the target detection algorithms in the scenes for which the correlation matrix R is extensively trained. Otherwise, the correlation matrix needs to be estimated by using the captured hyperspectral image.…”

“…The performance and resource utilization comparisons with the current stateof-the-art SBS-CEM [11] and DPBS-CEM [12] implementations are also per- 8 shows the number of clock cycles, operating frequencies and processing times for SBS-CEM [11], DPBS-CEM [12], ACE-R codesign [7] and the proposed implementation for processing the full HyMap image data set of 425 224000 pixels. The DPBS-CEM implementation requires the lowest number of clock cycles.…”

“…Each of these scanning orders provide different computational complexity for processing of hyperspectral data [5,6], in particular when the data streaming order differs from the processing order. The proposed work, built upon the hardware/software codesign presented in [7], introduces design and integration of a fully FPGA-based solution through implementation…”