2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) 2019
DOI: 10.1109/coolchips.2019.8721344
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Hybrid Access in Storage-class Memory-aware Low Power Virtual Memory System

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“…Here, the authors determined processes memory usage, but not in connection to CPU and DRAM memory usage. Also, Shirota et al (2019) developed hybrid access to memory hierarchical control mechanism, which adaptively alternated between SCM-aware low power Aggressive Paging (AP) with a small Dynamic Random-Access Memory (DRAM) as cache and direct access to memory bus coupled byte-addressable SCM. Using an optimal control prediction model created by ML, the study proposed an auto-tuning framework that dynamically determined the optimal control and optimal DRAM size when AP is selected.…”
Section: Memory Consumptionmentioning
confidence: 99%
“…Here, the authors determined processes memory usage, but not in connection to CPU and DRAM memory usage. Also, Shirota et al (2019) developed hybrid access to memory hierarchical control mechanism, which adaptively alternated between SCM-aware low power Aggressive Paging (AP) with a small Dynamic Random-Access Memory (DRAM) as cache and direct access to memory bus coupled byte-addressable SCM. Using an optimal control prediction model created by ML, the study proposed an auto-tuning framework that dynamically determined the optimal control and optimal DRAM size when AP is selected.…”
Section: Memory Consumptionmentioning
confidence: 99%