Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

Denq, Li-Ming; Hsing, Yu-Tsao; Wu, Cheng‐Wen

doi:10.1109/mdt.2009.37

Cited by 11 publications

(9 citation statements)

References 11 publications

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“…The area overhead for 8 256×64-bit memories is only about 0.89%. Subsequently, we compare the proposed pipelined BIST scheme with existing memory BISTs [8], [11], [18]- [20]. Table III summarizes comparison results of the area and test time complexity.…”

Section: Analysis and Resultsmentioning

confidence: 99%

“…Table IV summarizes the comparison results of area cost, where the area of the BIST schemes is estimated by physical layouts. The experimental results of the second, third, fourth, and fifth rows are from [11]. Also, all the BIST designs are used to test a chip with Table IV, the gate counts are estimated according to the synthesis results.…”

Section: Analysis and Resultsmentioning

confidence: 99%

“…Built-in self-test (BIST) approach has been widely used to test memory components in SOC designs [4]- [11]. The area cost of memory BIST circuits usually is small with respect to the area of the memories under test.…”

Section: Introductionmentioning

confidence: 99%

“…In [10], a shared BIST scheme was proposed to test multiple memories in parallel. To reduce the routing overhead, a hybrid BIST scheme was proposed in [11]. The hybrid BIST scheme uses a serial interface to control test pattern generators of the memories under test.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

Huang

2008

2008 17th Asian Test Symposium

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Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include a large amount of homogeneous memory cores (i.e., memory cores have the same size and configuration). This paper proposes a pipelined built-in self-test (PBIST) scheme for homogeneous memory cores in multicore SOCs. A PBIST circuit can be shared by clustered multiple homogeneous memories. This drastically reduces the hardware overhead of the PBIST circuit. A systematic procedure for converting a march test into a pipelined march test is also proposed. Experimental results show that the area overhead of a pipelined BIST for eight homogeneous 1k×128-bit memories is only about 0.71%.

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Section: Analysis and Resultsmentioning

confidence: 99%

Section: Analysis and Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

Huang

2008

2008 17th Asian Test Symposium

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“…Test data volume and power reduction can be achieved by utilizing a built-in self-test (BIST) [5][6][7], test compaction [8,9] and test compression techniques [3,4,[10][11][12][13][14][15][16][17][18][19][20][21][22]. However, BIST requires a longer test application time, and it is extensively used for memory testing but is not common for logic testing [17].…”

Section: Introductionmentioning

confidence: 99%

Test data compression using alternating variable run-length code

Zhao

Zhou

et al. 2011

Integration

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A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

Sruthi

2012

Progress in VLSI Design and Test

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Today's electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS'89 benchmark circuits.

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Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

Cited by 11 publications

References 11 publications

A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

Test data compression using alternating variable run-length code

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

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