Hybrid CNN-SVM Inference Accelerator on FPGA Using HLS

Liu, Bing; Zhou, Yanzhen; Feng, Lingfang; Fu, Hongshuo; Fu, Ping

doi:10.3390/electronics11142208

Cited by 8 publications

(4 citation statements)

References 14 publications

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“…Liu et al [28] introduce a CNN accelerator for both standard convolution and depthwise separable convolution, which can handle network layers of different scales. Liu et al [29] propose an accelerator that supports hybrid CNN-SVM algorithms. Ma et al [30] introduce a CNN accelerator that can handle different kinds of convolutions, especially irregular convolutions, and at the same time, they accelerate the networks by reducing the number of loops in the layers.…”

Section: Related Workmentioning

confidence: 99%

FPQNet: Fully Pipelined and Quantized CNN for Ultra-Low Latency Image Classification on FPGAs Using OpenCAPI

Ji,

Al-Ars,

Hofstee

et al. 2023

Electronics

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Convolutional neural networks (CNNs) are to be effective in many application domains, especially in the computer vision area. In order to achieve lower latency CNN processing, and reduce power consumption, developers are experimenting with using FPGAs to accelerate CNN processing in several applications. Current FPGA CNN accelerators usually use the same acceleration approaches as GPUs, where operations from different network layers are mapped to the same hardware units working in a multiplexed manner. This will result in high flexibility in implementing different types of CNNs; however, this will degrade the latency that accelerators can achieve. Alternatively, we can reduce the latency of the accelerator by pipelining the processing of consecutive layers, at the expense of more FPGA resources. The continued increase in hardware resources available in FPGAs makes such implementations feasible for latency-critical application domains. In this paper, we present FPQNet, a fully pipelined and quantized CNN FPGA implementation that is channel-parallel, layer-pipelined, and network-parallel, to decrease latency and increase throughput, combined with quantization methods to optimize hardware utilization. In addition, we optimize this hardware architecture for the HDMI timing standard to avoid extra hardware utilization. This makes it possible for the accelerator to handle video datasets. We present prototypes of the FPQNet CNN network implementations on an Alpha Data 9H7 FPGA, connected with an OpenCAPI interface, to demonstrate architecture capabilities. Results show that with a 250 MHz clock frequency, an optimized LeNet-5 design is able to achieve latencies as low as 9.32 µs with an accuracy of 98.8% on the MNIST dataset, making it feasible for utilization in high frame rate video processing applications. With 10 hardware kernels working concurrently, the throughput is as high as 1108 GOPs. The methods in this paper are suitable for many other CNNs. Our analysis shows that the latency of AlexNet, ZFNet, OverFeat-Fast, and OverFeat-Accurate can be as low as 69.27, 66.95, 182.98, and 132.6 µs, using the architecture introduced in this paper, respectively.

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Section: Related Workmentioning

confidence: 99%

FPQNet: Fully Pipelined and Quantized CNN for Ultra-Low Latency Image Classification on FPGAs Using OpenCAPI

Ji,

Al-Ars,

Hofstee

et al. 2023

Electronics

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“…Some scholars based their work on quantization technology in order to reduce the amount of neural network data, so as to accelerate the calculation of face direction recognition [149]. Referenced [150] designed FPGA accelerators from the perspective of reusing hardware resources, so as to reduce the utilization of FPGA resources.…”

Section: Fpga Accelerator For Speech Recognitionmentioning

confidence: 99%

A Review of the Optimal Design of Neural Networks Based on FPGA

Wang

Luo

2022

Applied Sciences

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Deep learning based on neural networks has been widely used in image recognition, speech recognition, natural language processing, automatic driving, and other fields and has made breakthrough progress. FPGA stands out in the field of accelerated deep learning with its advantages such as flexible architecture and logic units, high energy efficiency ratio, strong compatibility, and low delay. In order to track the latest research results of neural network optimization technology based on FPGA in time and to keep abreast of current research hotspots and application fields, the related technologies and research contents are reviewed. This paper introduces the development history and application fields of some representative neural networks and points out the importance of studying deep learning technology, as well as the reasons and advantages of using FPGA to accelerate deep learning. Several common neural network models are introduced. Moreover, this paper reviews the current mainstream FPGA-based neural network acceleration technology, method, accelerator, and acceleration framework design and the latest research status, pointing out the current FPGA-based neural network application facing difficulties and the corresponding solutions, as well as prospecting the future research directions. We hope that this work can provide insightful research ideas for the researchers engaged in the field of neural network acceleration based on FPGA.

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“…With the vigorous development of the field of machine learning, algorithms such as support vector machines [11], random forests [12], and KNN [13] are gradually applied to the field of power transformer fault diagnosis. Support vector machines have been widely used due to their high accuracy and generalization performance [14].…”

Section: Introductionmentioning

confidence: 99%

Improved Support Vector Machine for Voiceprint Diagnosis of Typical Faults in Power Transformers

et al. 2023

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The traditional power transformer diagnosis method relies on a lot of experience knowledge and a complex sampling process, which brings great difficulties to the fault diagnosis work. To solve this problem, a fault feature extraction method based on fully adaptive noise set empirical mode decomposition (CEEMDAN) is proposed, and the hunter–prey optimization (HPO) algorithm is used to optimize the support vector machine (SVM) to identify and classify the voice print faults of power transformers. Firstly, the CEEMDAN algorithm is used to decompose the voicemarks into several IMF components. IMF components containing fault information are selected according to the envelope kurtosis index and reconstructed to generate new signal sequences. PCA dimensionality reduction is performed on the reconstructed signal, and the principal components are extracted with a high cumulative contribution rate as input to SVM. Then, the HPO-SVM algorithm is used to classify and identify transformer faults. Apply the proposed method to the diagnosis of typical faults in power transformers. The results show that the accuracy of this method in identifying various fault states of power transformers can reach 98.5%, and it has better classification performance than other similar methods.

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Hybrid CNN-SVM Inference Accelerator on FPGA Using HLS

Cited by 8 publications

References 14 publications

FPQNet: Fully Pipelined and Quantized CNN for Ultra-Low Latency Image Classification on FPGAs Using OpenCAPI

FPQNet: Fully Pipelined and Quantized CNN for Ultra-Low Latency Image Classification on FPGAs Using OpenCAPI

A Review of the Optimal Design of Neural Networks Based on FPGA

Improved Support Vector Machine for Voiceprint Diagnosis of Typical Faults in Power Transformers

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