Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs

Sharifi,; Coskun,; Rosing,

doi:10.1109/aspdac.2010.5419681

Cited by 40 publications

(22 citation statements)

References 25 publications

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“…Using this tool, we measured the average temperature using a floorplan and silicon chip area similar to the ARM Cortex A9 processor [4]. We ran thermal simulations and sampled the application's power consumption at 10 ms intervals, similar to modern operating systems (e.g., Linux) [35]. Previous work showed that this fine-grained sampling accurately depicted the application's temperature characteristics during execution [35].…”

Section: Methodsmentioning

confidence: 99%

“…We ran thermal simulations and sampled the application's power consumption at 10 ms intervals, similar to modern operating systems (e.g., Linux) [35]. Previous work showed that this fine-grained sampling accurately depicted the application's temperature characteristics during execution [35]. To model an embedded system without cooling mechanisms, such as a heat sink and/or spreader, we set the convection resistance to 4K/W and the heat sink and spreader thickness to 1 mm and 0.1 mm, respectively; these values are considered negligible in Hotspot.…”

Section: Methodsmentioning

confidence: 99%

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TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Adegbija

Gordon‐Ross

2017

Computers

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Embedded systems have stringent design constraints, which has necessitated much prior research focus on optimizing energy consumption and/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature optimization, is an emergent concern. Most embedded systems only dissipate heat by passive convection, due to the absence of dedicated thermal management hardware mechanisms. The embedded system's temperature not only affects the system's reliability, but can also affect the performance, power, and cost. Thus, embedded systems require efficient thermal management techniques. However, thermal management can conflict with other optimization objectives, such as execution time and energy consumption. In this paper, we focus on managing the temperature using a synergy of cache optimization and dynamic frequency scaling, while also optimizing the execution time and energy consumption. This paper provides new insights on the impact of cache parameters on efficient temperature-aware cache tuning heuristics. In addition, we present temperature-aware phase-based tuning, TaPT, which determines Pareto optimal clock frequency and cache configurations for fine-grained execution time, energy, and temperature tradeoffs. TaPT enables autonomous system optimization and also allows designers to specify temperature constraints and optimization priorities. Experiments show that TaPT can effectively reduce execution time, energy, and temperature, while imposing minimal hardware overhead.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Adegbija

Gordon‐Ross

2017

Computers

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“…In [7], an approach is proposed for asymmetric dual core designs where the workload is off-loaded to the low power core in order to reduce the occurrence of thermal emergencies with low performance impact. In [13], a centralized approach is proposed for temperature and energy management in heterogeneous MPSoCs. This approach is called hybrid in the sense that the scheduler has two different modes which are selected based on the workload utilization.…”

Section: Related Workmentioning

confidence: 99%

Temperature-Aware Scheduling for Embedded Heterogeneous MPSoCs with Special Purpose IP Cores

Sharifi

Rosing

2011

2011 Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN)

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Many embedded heterogeneous MPSoCs integrate general purpose cores along with special purpose cores. The power states of these cores are usually controlled by an internal hardware controller rather than the central operating system. In this paper, we propose a thermal management technique which reduces the performance penalty of central thermal management by considering these special purpose cores and the performance requirements of the tasks running on them. Our experimental results show that for the workloads with high priority special purpose tasks, our technique can reduce the occurence of thermal violations by at least 3X while improving the weighted execution time by up to 24%.

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“…Relatively little work has focused on heterogeneous embedded MPSoCs. A method is proposed in [28] for energy and temperature aware scheduling of embedded workloads on heterogeneous MPSoCs where decisions on either energy savings or thermal management operating mode of the scheduler and the frequency settings of the cores are made based on the performance requirements of the workload which are estimated at runtime.…”

Section: Introductionmentioning

confidence: 99%

TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs

Sharifi¹,

Ayoub²,

Rosing³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Heterogeneous Multi-Processor Systems on a Chip (MPSoCs) are more complex from a thermal perspective compared to the homogeneous MPSoCs because of their inherent imbalance in power density. In this work we develop TempoMP, a new technique for thermal management of heterogeneous MPSoCs which leverages multi-parametric optimization along with our novel thermal predictor, Tempo. TempoMP is able to deliver locally optimal dynamic thermal management decisions to meet thermal constraints while minimizing power and maximizing performance. It leverages our Tempo predictor which, unlike the previous techniques, can estimate the impact of future power state changes at negligible overhead. Our experiments show that compared to the state of the art, Tempo can reduce the maximum prediction error by up to an order of magnitude. Our experiments with heterogeneous MPSoCs also show that TempoMP meets thermal constraints while reducing the average task lateness by 2.5X and energy-lateness product by 5X compared to the state of the art techniques. I. IntroductionHeterogeneous MPSoCs integrate cores of various performance and power characteristics to provide a better tradeoff with respect to performance, power and temperature by allowing customization of performance and power of the chip to match the requirements of the workload. uses ARMA model which has to be updated at run time to avoid inaccuracies due to workload changes, thus leading to overhead. A few techniques have been proposed that do not require online adaptation, such as [19] and [5], but both assume that previous thermal history is a good estimate of future thermal behavior, and thus neglect the impact of future power state changes on temperature. Proactive thermal management algorithms that leverage these predictors are heuristic in nature.A number of thermal management techniques have been proposed that leverage control theory and optimization. In [25], convex optimization is used to control the frequency of the cores on a homogeneous MPSoC to guaranty that thermal constraints are met. In [33], a linear quadratic regulator is used to solve the frequency assignment problem

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Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs

Cited by 40 publications

References 25 publications

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Temperature-Aware Scheduling for Embedded Heterogeneous MPSoCs with Special Purpose IP Cores

TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs

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