Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology

Blomme, Pieter; Cacciato, A.; Wellekens, D.; Breuil, L.; Rosmeulen, M.; Kar, Gouri Sankar; Locorotondo, S.; Vrancken, C.; Richard, Olivier; Debusschere, I.; Houdt, J. Van

doi:10.1109/led.2011.2181152

Cited by 28 publications

(18 citation statements)

References 10 publications

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“…The stacks were then submitted to a 1 min N 2 annealing (post-deposition anneal, PDA). Our previous experience showed that the optimal PDA condition for Al 2 O 3 is 1000 °C [3]. Therefore, for HfO 2 -Al 2 O 3 stacks, the 1000 °C PDA step was applied after each Al 2 O 3 deposition (Table I).…”

Section: Methodsmentioning

confidence: 99%

“…The use of metals combined with high permittivity materials in a Si\metal\dielectric\metal\poly-Si stack enables the scaling of the FG beyond 20 nm. The proof of concept has been realized with 50-nm HFG CMOS integrated memory cells using TiN as the metal layers and Al 2 O 3 as the dielectric [3][4]. However, for further scaling one also needs to reduce the equivalent oxide thickness (EOT) of the cell [5].…”

Section: Introductionmentioning

confidence: 99%

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High-k dielectrics for hybrid floating gate memory applications

et al. 2012

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We report on the materials issues involved in the hybrid floating gate (HFG) device fabrication, where the interpoly dielectric is replaced by an intermetal dielectric (IMD). Indeed, in HFG the dielectric is inserted in between two metal layers in a metal\dielectric\metal stack. The materials of choice were TiN as the metal layer and Al 2 O 3 and HfO 2 (and their combination) as IMD. The program/erase performance is discussed based on the dielectric constant and crystallinity of the IMD and the metal-IMD interface characteristics.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-k dielectrics for hybrid floating gate memory applications

et al. 2012

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“…The HFG concept has been proven using 6 nm TiN (WF 4.7 eV) as the metal layer and 17 nm Al 2 O 3 (k-value ~9; EOT ~ 7 nm) as IGD (3). Optimal performance has been obtained when Al 2 O 3 is annealed after deposition at 1000 °C (3). For that conditions, the TiN\Al 2 O 3 cell is characterized by a PW of ~4 V and a charge loss of 0.08 V after 24 h at 85 °C (retention) ( Fig.…”

Section: Introductionmentioning

confidence: 99%

(Invited) High-k Dielectrics and High Work Function Metals for Hybrid Floating Gate NAND Flash Applications

Lisoni¹,

Breuil²,

Blomme³

et al. 2014

ECS Trans.

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In this paper we will discuss the key materials issues involved in the successful fabrication of hybrid floating gate (HFG) devices, a solution to scale NAND flash below 20 nm node. In HFG a Si\metal stack replaces the standard poly-Si FG. The metal is required to have a high work function (WF) in order to control the leakage through the inter-gate dielectric (IGD); a high k-value of the IGD is essential to increase the coupling factor of the memory cell. Our reference stack uses TiN(WF 4.7 eV) and Al 2 O 3 (k~9)

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“…The experimentally determined programming saturation (line with markers) confirms the tendency from the predictions (line without markers) that are based on simulated programming saturation (simulating the current through the IPD using the approach of [9], combined with the current through the tunnel oxide, after fitting the simulation parameters to capacitor measurements). point, we need to determine when the ISPP curve starts deviating from the ideal slope, as this indicates the onset of charge trapping in the IGD dielectric [8]. This saturation point becomes apparent after shifting the ISPP curves towards the same programming voltage, and comparing with the behaviour of the high-CR device (where all 8 WL are used), as shown in figure 8.…”

Section: Resultsmentioning

confidence: 99%

“…As the coupling ratio drops, the programming voltage increases, and the portion of the ISPP curve where the slope deviates from ideal increases. No hard saturation being observed, this indicates that programming continues through charge trapping in the IGD after the IGD leakage current reaches the tunnel dielectric current level [8].…”

Section: Device Operationmentioning

confidence: 92%

Experimental study of programming saturation in low-coupling planar high-k/metal gate nand flash memory cells using a dedicated test structure

Blomme

Tan

Souriau

et al. 2014

2014 IEEE 6th International Memory Workshop (IMW)

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Fully planar NAND Flash arrays operate with very low coupling ratio (CR), and the CR reduces even further when scaling below 20 nm half-pitch. As a consequence, they suffer from programming saturation due to excessive leakage through the intergate dielectic (IGD) if no special precautions (such as the use of high-k IGD or hybrid floating gate) are taken. In this work, we investigate the dependence on the coupling ratio of programming saturation by using a dedicated test structure: by using a device with 8 wordlines sharing the same floating gate (FG), it is possible to program this device with any arbitrarily reduced effective coupling ratio, showing which programming window can be achieved.We demonstrate that the used devices with polySi\TiN FG and HfAlO\Al2O3\HfAlO IGD stack are suitable for operation with a coupling ratio down to 35% with 4V programming window above the fresh Vth. This coupling ratio corresponds to fully planar memory cells with 10 nm half-pitch, showing that programming saturation is not a showstopper for scaling down to 10nm node fully planar Flash memory cells.

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Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology

Cited by 28 publications

References 10 publications

High-k dielectrics for hybrid floating gate memory applications

High-k dielectrics for hybrid floating gate memory applications

(Invited) High-k Dielectrics and High Work Function Metals for Hybrid Floating Gate NAND Flash Applications

Experimental study of programming saturation in low-coupling planar high-k/metal gate nand flash memory cells using a dedicated test structure

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