Hybrid Functional and Instruction Level Power Modeling for Embedded Processors

Blume, Holger; Becker, Daniel; Botteck, Martin; Brakensiek, J.; Noll, Tobias G.

doi:10.1007/11796435_23

Cited by 10 publications

(8 citation statements)

References 5 publications

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“…4) Hybrid FLPA/ALPA: In order to obtain a good trade-off between the estimation accuracy and the modeling complexity, a hybrid FLPA(functional level power analysis) and ILPA(instruction level power analysis) model [15] is elaborated which advantageously combines the lower modeling and computational efforts of an FLPA model and the higher accuracy of an ILPA model. The trade-off is further explained in [16] with a 3-D LUT and a tripartite hyper-graph.…”

Section: A Prior Workmentioning

confidence: 99%

Power modeling and estimation during ADL-driven embedded processor design

Wang

Xie

et al. 2013

2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

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Rising concern for thermal stress and tight energy constraints have forced designers to consider power as a design criterion from early design phase. Despite many advances in highlevel power estimation techniques, there is a lack of generic power estimation capabilities in prominent high-level design flows. In this paper we propose power modeling and estimation techniques during Architecture Description Language (ADL)-based high-level embedded processor design. The first technique is based on accurate switching activity extraction from cycle-accurate instruction-set simulation. The second technique is developed through unit-level power modeling for ADL architecture construct. Multivariate linear regression is used to characterize the unit power model. Experiments are performed on a RISC processor using state-of-the-art high-level processor design flow to demonstrate the accuracy and efficiency of the proposed techniques.

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Section: A Prior Workmentioning

confidence: 99%

Power modeling and estimation during ADL-driven embedded processor design

Wang

Xie

et al. 2013

2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

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“…McPAT [110] models all dynamic, static and short-circuit power while providing joint modelling capability of area and timing. To increase modelling accuracy, a hybrid FLPA(functional level power analysis) and ILPA(instruction level power analysis) model [24] is elaborated which advantageously combines the lower modelling and computational efforts of an FLPA model and the higher accuracy of an ILPA model. The trade-off is further explained in [139] with a 3-D LUT and a tripartite hyper-graph.…”

Section: High-level Processor Power/thermal/delay Joint Modelling Framentioning

confidence: 99%

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Zheng¹,

Noll²,

Chattopadhyay³

2018

Computer Architecture and Design Methodologies

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This thesis is the result of my work as research assistant at the Institute for Communication Technologies and Embedded Systems (ICE) at the RWTH Aachen University. During this time I have been accompanied and supported by many people. It is my great pleasure to take this opportunity to thank them. My most sincere thanks go to my advisors, Prof. Anupam Chattopadhyay and Prof. Tobias Noll. Anupam has been extremely helpful and tremendously inspiring throughout my PhD study. Prof. Noll has been impressively knowledgeable while patient with my ideas and mistakes. Their thoughtful advices have greatly contributed to this work and influenced me for my future career. Special thanks go to my defense committee members, Prof. Andrei Vescan and Prof. Renato Negra for spending their time, offering oral exam, giving me feedback, and attending my defense session. Several colleagues in ICE and EECS have assisted and encouraged me during the past five years for my work and personal life. Among them I would like to show my deep appreciation to Ayesha Khalid, Zoltán Rákossy and Michael Meixner. Furthermore, I would like to thank my students

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“…An energy estimator was used in [17] for exploring different CGA interconnect architectures which is complementary to our work and we would like to integrate it to our framework in our future work. In [18] a hybrid functional and instruction level power model has been proposed. However it is mainly targeting the embedded general purpose RISC processors such as ARM.…”

Section: Related Workmentioning

confidence: 99%

Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications

Palkovic

Hartmann

Allam

et al. 2010

2010 IEEE Workshop on Signal Processing Systems

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The power consumption is a key aspect when designing a handheld device. Even when cycle accurate instruction set simulators for the ASIPs used in SDRs are existing to evaluate the performance of given mapping, the power consumption is evaluated only in the later phase during gate-level simulation.In this paper we propose an automatic way how to obtain dynamic energy consumption per opcode activation of an ASIP baseband-processor of our SDR platform. We use the results obtained for time-space energy consumption modeling of dynamic reconfigurable CGA processor datapath at the instruction set simulator level that we demonstrate on WLAN 2x2 40MHz application. The results allow us to propose important application and architectural changes for our ASIP.

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Hybrid Functional and Instruction Level Power Modeling for Embedded Processors

Cited by 10 publications

References 5 publications

Power modeling and estimation during ADL-driven embedded processor design

Power modeling and estimation during ADL-driven embedded processor design

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications

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