Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

Zhang, Xuexiang; Yao, Jiaxin; Luo, Yanna; Cao, Lei; Zheng, Yantong; Zhang, Qingzhu; Wu, Zhenhua; Yin, Huaxiang

doi:10.1109/ted.2024.3358251

IEEE Trans. Electron Devices

2024

DOI: 10.1109/ted.2024.3358251

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Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

Xuexiang Zhang,

Jiaxin Yao,

Yanna Luo

et al.

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2024

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Cited by 2 publications

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Stacked Gate-All-Around Nanosheet Transistors with Full-Air-Spacers for Reducing Parasitic Capacitance to Improve Device and Circuit Performance

Li,

Cao,

Zhang

et al. 2024

Microelectronics Journal

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Stacked Gate-All-Around Nanosheet Transistors with Full-Air-Spacers for Reducing Parasitic Capacitance to Improve Device and Circuit Performance

Li,

Cao,

Zhang

et al. 2024

Microelectronics Journal

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Low‐temperature SOI SiGe/Si superlattice FinFET with omega‐shaped channel and self‐allied silicide for 3D sequential IC

Qin,

Sang,

Cao

et al. 2024

Electronics Letters

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In this letter, to improve the performance and reduce leakage currents of bulk low‐temperature multi‐layer SiGe/Si superlattice (SL) fin field‐effect transistors (FinFETs), a p‐type omega‐shaped channel (Ω‐channel) SL FinFET is realized by etching a Si/Si0.7Ge0.3 triple‐layer stacked structure in a replacement metal gate (RMG) module on a silicon‐on‐insulator (SOI) substrate. In addition, a self‐allied Ni0.9Pt0.1 silicide process and a low‐thermal‐budget (≤400°C) integration procedure were performed on the Ω‐channel SL FinFET. Test results demonstrate that the on‐state current (Ion) is increased by 5.5 times (from 78 to 429 µA/µm) and the off‐state current (Ioff) is reduced by 78.8% (from 5.2 × 10−3 to 1.1 × 10−3 µA/µm) when compared with the corresponding currents of traditional bulk SL FinFETs.

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Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

Cited by 2 publications

References 34 publications

Stacked Gate-All-Around Nanosheet Transistors with Full-Air-Spacers for Reducing Parasitic Capacitance to Improve Device and Circuit Performance

Stacked Gate-All-Around Nanosheet Transistors with Full-Air-Spacers for Reducing Parasitic Capacitance to Improve Device and Circuit Performance

Low‐temperature SOI SiGe/Si superlattice FinFET with omega‐shaped channel and self‐allied silicide for 3D sequential IC

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