Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Abstract

Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

HLS and FPGA-Powered Streaming Video Encoder Accelerator for IoTs Edge Computing

“…Upon optimizing and generating HDL-based hardware descriptions for the four accelerator cores, we proceed to construct our testing system based on the hardware accelerator computing paradigm [3]. In our case study, we employ the Xilinx MPSoC Ultra96v2 edge computing board [20] as the evaluation platform.…”

“…Subsequently, we employ High-Level Synthesis (HLS) tools to leverage various optimizations, such as loop unrolling or pipelining, to generate the most optimized accelerator core. Finally, the system is constructed based on the hardware accelerator architecture [3], aiming to capitalize on the advantages offered by both generalpurpose processors and FPGA-based accelerator cores.…”

An FPGA-based Convolution IP Core for Deep Neural Networks Acceleration

“…To overcome this obstacle, we use FPGA-based hardware accelerator platforms for edge computing devices where we can exploit the computation flexibility of host processors as well as the high performance of reconfigurable fabrics [2,3]. Furthermore, although FPGAs suffer from low working frequency, they outperform GPUs in energy consumption and provide higher performance and energy-efficient than CPUs [4]. Therefore, an FPGA-based hardware accelerator is a promising approach for building high-performance DNN in edge devices.…”

Efficient Random Forest Acceleration for Edge Computing Platforms with FPGA Technology

“…The Xilinx PYNQ-Z2 edge computing platform with a Xilinx MPSoC Zynq FPGA device [6] is used to build a testing system based on the hardware accelerator paradigm [7]. The proposed architecture is implemented on the FPGA fabrics, while the ARM-hardwired processor is responsible for preprocessing data and determining the final results based on random forest computation.…”