Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies

Abstract

In this work, hybrid low-dropout voltage regulators (LDO) designed with a TFET-MOSFET nanowire (NW) technologies are presented. The devices were modeled using Verilog-A with lookup tables based on experimental data of NW-TFETs and NW-MOSFETs fabricated in the same silicon vertical process flow. In all LDOs, the amplifier devices were biased with the same gm/ID = 9.5 V-1 for a maximum load current/capacitance of 1 mA/1 nF. In the hybrid regulators, the power transistors are designed with NW-MOSFETs to deliver the high load current, while the other devices are implemented with NW-TFET to provide high gain and low power consumption. Due to different onset voltages, two hybrid LDOs are proposed, one with symmetrical onset voltages implemented with a voltage shift (Hybrid-ΔV LDO) and one with a level-shift stage using the real characteristics of the devices (Hybrid-LS LDO). The hybrid circuits were compared to LDOs designed using only NW-TFETs and with only NW-MOSFETs. The Hybrid-ΔV LDO presents the best loop gain (62 dB) with a low quiescent current (7 nA), while the Hybrid-LS LDO shows a good gain-bandwidth product (700 Hz). In the transient analysis, the hybrid circuits showed a settling time close to the NW-MOSFET
LDO but with higher undershoot/overshoot values in the case of a load transient. As demonstrated, the use of hybrid projects with TFET-MOSFET nanowire technologies enable LDOs with ultra-low power consumption and high loop gain, that are presented on TFET circuits and with a frequency response equivalent of MOSFET circuits.