2018
DOI: 10.1109/tvlsi.2018.2832607
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Hybrid Monolithic 3-D IC Floorplanner

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Cited by 12 publications
(3 citation statements)
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“…We implement components of SPRING at the register-transfer level (RTL) with SystemVerilog to estimate delay, power, and area. The RTL design is synthesized by Design Compiler [59] using a 14nm FinFET technology library [60]. Floorplanning is done by Capo [61], an open-source floorplacer.…”
Section: Simulation Methodologymentioning
confidence: 99%
“…We implement components of SPRING at the register-transfer level (RTL) with SystemVerilog to estimate delay, power, and area. The RTL design is synthesized by Design Compiler [59] using a 14nm FinFET technology library [60]. Floorplanning is done by Capo [61], an open-source floorplacer.…”
Section: Simulation Methodologymentioning
confidence: 99%
“…We implement different modules presented above at the register-transfer level (RTL) with SystemVerilog. Design Compiler [35] synthesizes the RTL design using a 14nm FinFET technology library [36]. Capo [37], an open-source floorplacer, performs floorplanning.…”
Section: ) Dynamic Inference Modulesmentioning
confidence: 99%
“…The authors of [15] proposed a floorplanner for hybrid monolithic 3D ICs, which shows significant area saving and power reduction in the OpenSPARC T2 processor. However, this approach cannot be directly used to implement logic-onmemory M3D ICs, because it handles gate-level monolithic logic and block-level monolithic memory on different tiers separately.…”
Section: Limitations Of Existing 3d Pandr Flowsmentioning
confidence: 99%